ATE136134T1 - Vorrichtung und verfahren zur fehlererkennung in das ergebnis einer arithmetische operation - Google Patents

Vorrichtung und verfahren zur fehlererkennung in das ergebnis einer arithmetische operation

Info

Publication number
ATE136134T1
ATE136134T1 AT89310634T AT89310634T ATE136134T1 AT E136134 T1 ATE136134 T1 AT E136134T1 AT 89310634 T AT89310634 T AT 89310634T AT 89310634 T AT89310634 T AT 89310634T AT E136134 T1 ATE136134 T1 AT E136134T1
Authority
AT
Austria
Prior art keywords
digits
operands
added
another
result
Prior art date
Application number
AT89310634T
Other languages
English (en)
Inventor
Safdar Mahmood Asghar
John Gray Bartkowiak
Eric Allen Suss
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE136134T1 publication Critical patent/ATE136134T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1497—Details of time redundant execution on a single processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/104—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Hardware Redundancy (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Retry When Errors Occur (AREA)
AT89310634T 1988-10-26 1989-10-17 Vorrichtung und verfahren zur fehlererkennung in das ergebnis einer arithmetische operation ATE136134T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/262,658 US4994993A (en) 1988-10-26 1988-10-26 System for detecting and correcting errors generated by arithmetic logic units

Publications (1)

Publication Number Publication Date
ATE136134T1 true ATE136134T1 (de) 1996-04-15

Family

ID=22998460

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89310634T ATE136134T1 (de) 1988-10-26 1989-10-17 Vorrichtung und verfahren zur fehlererkennung in das ergebnis einer arithmetische operation

Country Status (5)

Country Link
US (1) US4994993A (de)
EP (1) EP0366331B1 (de)
JP (1) JPH02178738A (de)
AT (1) ATE136134T1 (de)
DE (1) DE68926093T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5535228A (en) * 1993-02-19 1996-07-09 Motorola, Inc. Device and method for achieving rotational invariance in a multi-level trellis coding system
US5351046A (en) * 1993-05-28 1994-09-27 Adcox Thomas A Method and system for compacting binary coded decimal data
DE4406391C1 (de) * 1994-02-26 1995-03-16 Bosch Gmbh Robert Elektronisches Rechenwerk
RU2005129281A (ru) 2003-03-20 2006-01-27 Арм Лимитед (Gb) Система памяти, имеющая механизмы быстрого и медленного считывания данных
US8650470B2 (en) 2003-03-20 2014-02-11 Arm Limited Error recovery within integrated circuit
US8185812B2 (en) 2003-03-20 2012-05-22 Arm Limited Single event upset error detection within an integrated circuit
DE602004001869T2 (de) 2003-03-20 2007-05-03 Arm Ltd., Cherry Hinton Fehlererkennung und fehlerbehebung für systematische und zufällige fehler innerhalb einer verarbeitungsstufe einer integrierten schaltung
US7278080B2 (en) * 2003-03-20 2007-10-02 Arm Limited Error detection and recovery within processing stages of an integrated circuit
US7203885B2 (en) * 2003-09-30 2007-04-10 Rockwell Automation Technologies, Inc. Safety protocol for industrial controller
US8347165B2 (en) 2007-12-17 2013-01-01 Micron Technology, Inc. Self-timed error correcting code evaluation system and method
US8171386B2 (en) 2008-03-27 2012-05-01 Arm Limited Single event upset error detection within sequential storage circuitry of an integrated circuit
US8055697B2 (en) * 2008-03-28 2011-11-08 Intel Corporation Method and device for dynamically verifying a processor architecture
US8161367B2 (en) 2008-10-07 2012-04-17 Arm Limited Correction of single event upset error within sequential storage circuitry of an integrated circuit
US8493120B2 (en) 2011-03-10 2013-07-23 Arm Limited Storage circuitry and method with increased resilience to single event upsets
US8806316B2 (en) 2012-01-11 2014-08-12 Micron Technology, Inc. Circuits, integrated circuits, and methods for interleaved parity computation
JP5850016B2 (ja) * 2013-10-02 2016-02-03 横河電機株式会社 フィールド機器

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL91958C (de) * 1949-06-22
US2861744A (en) * 1955-06-01 1958-11-25 Rca Corp Verification system
US3098994A (en) * 1956-10-26 1963-07-23 Itt Self checking digital computer system
NL230983A (de) * 1957-09-03
NL250876A (de) * 1959-05-11
US3660646A (en) * 1970-09-22 1972-05-02 Ibm Checking by pseudoduplication
US3816728A (en) * 1972-12-14 1974-06-11 Ibm Modulo 9 residue generating and checking circuit
US3814923A (en) * 1973-01-02 1974-06-04 Bell Telephone Labor Inc Error detection system
US4181969A (en) * 1978-01-18 1980-01-01 Westinghouse Electric Corp. System for detecting and isolating static bit faults in a network of arithmetic units
GB2033115B (en) * 1978-09-25 1982-11-10 Burtsev V Apparatus for detecting and correcting errors in arithmetic processing of data represented in the numerical system of residual classes
JPS60140422A (ja) * 1983-12-28 1985-07-25 Nec Corp 演算処理装置

Also Published As

Publication number Publication date
DE68926093T2 (de) 1996-10-31
EP0366331B1 (de) 1996-03-27
JPH02178738A (ja) 1990-07-11
US4994993A (en) 1991-02-19
EP0366331A2 (de) 1990-05-02
DE68926093D1 (de) 1996-05-02
EP0366331A3 (de) 1992-05-13

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