JPS6477958A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS6477958A
JPS6477958A JP23529187A JP23529187A JPS6477958A JP S6477958 A JPS6477958 A JP S6477958A JP 23529187 A JP23529187 A JP 23529187A JP 23529187 A JP23529187 A JP 23529187A JP S6477958 A JPS6477958 A JP S6477958A
Authority
JP
Japan
Prior art keywords
phosphor
gate electrodes
layers
piled
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23529187A
Other languages
Japanese (ja)
Inventor
Hiroyuki Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23529187A priority Critical patent/JPS6477958A/en
Publication of JPS6477958A publication Critical patent/JPS6477958A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Abstract

PURPOSE:To make it needless to arrange a diffusion layer between neighboring gate electrodes in order and to promote high integration, by forming the first electrode regions of the first phosphor-containing polycrystalline silicon layers and forming an oxide film, followed by burying the second phosphor-containing polycrystalline silicon layers between the first electrode regions. CONSTITUTION:The first phospor-containing polysilicon layers 6 are formed. Then, the first insulating films 8 are piled up and the first gate electrodes 6a-6d are formed. Further, an oxide film 12 is formed, the second phosphor- containing polysilicon layers 13 are piled up while making these second phosphor-containing polysilicon layers 13 to remain only in the gaps 11a-11d. Thereby, the second gate electrodes 15a-15d are formed. High integration of longitudinal--piling type MCS transistors can be performed because of no existing diffusion layers between the neighboring gate electrodes.
JP23529187A 1987-09-19 1987-09-19 Semiconductor device and manufacture thereof Pending JPS6477958A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23529187A JPS6477958A (en) 1987-09-19 1987-09-19 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23529187A JPS6477958A (en) 1987-09-19 1987-09-19 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS6477958A true JPS6477958A (en) 1989-03-23

Family

ID=16983934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23529187A Pending JPS6477958A (en) 1987-09-19 1987-09-19 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6477958A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6198137B1 (en) * 1998-10-30 2001-03-06 Sharp Kabushiki Kaisha Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6198137B1 (en) * 1998-10-30 2001-03-06 Sharp Kabushiki Kaisha Semiconductor device

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