JPS6476117A - Normalization multiplier - Google Patents

Abstract

PURPOSE:To obtain a multiplication result normalized equally by the maximum value of a multiplier by multiplying the data to add 1 to a two-fold multiplicand and a multiplier factor and executing the correction by an adder circuit. CONSTITUTION:When a lower-most bit Io of an input terminal 111 of a 7-bit length is excluded, a multiplicand A10 of a 6-bit length is shifted by one bit, supplied to an input terminal 111 as it is and an a(=1) is supplied, an input circuit 1 is composed. A multiplier B12 is supplied to an input terminal 121. Thus, respective inputs of a multiplying circuit 2 is 7 bits, the lower order 6 bits are neglected, and therefore, a multiplication result C13 becomes a formula {(2A+1)XB}divided by 64. Further, the formula becomes the input of an adder circuit 3, b(=1) is added in the adder circuit 3, 6 bits are removed from the upper-most order bit for the output, and therefore, a multiplication result D14 of the normalization multiplier becomes a formula {(2A+1)XB}divided by 2. Thus, a satisfactorily normalized multiplication can be obtained.