JPS5599649A - Digital multiplier - Google Patents

Digital multiplier

Info

Publication number
JPS5599649A
JPS5599649A JP795379A JP795379A JPS5599649A JP S5599649 A JPS5599649 A JP S5599649A JP 795379 A JP795379 A JP 795379A JP 795379 A JP795379 A JP 795379A JP S5599649 A JPS5599649 A JP S5599649A
Authority
JP
Japan
Prior art keywords
multiplier
output
adder
added
multiplication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP795379A
Other languages
Japanese (ja)
Other versions
JPS6122328B2 (en
Inventor
Kenji Nakayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP795379A priority Critical patent/JPS5599649A/en
Publication of JPS5599649A publication Critical patent/JPS5599649A/en
Publication of JPS6122328B2 publication Critical patent/JPS6122328B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To realize the digital multiplier with the circuit scale of about 3/4 by giving the multiplication to input X with dissolution into the higher-rank and lower- rank bits.
CONSTITUTION: Input X sent from terminal 11 is divided into higher-rank bit X0 and lower-rank bit X1 through divider circuit 12. For bit X1, A1+KA0 is multiplied at multiplier 13. At the same time, X1 is added by X0 via adder 14, and the output undergoes the multiplication of A0 at multiplier 15. Then bit X0 is multiplied by A1WA0 by multiplier 16. The output of multiplier 15 undergoes the multiplication of -K at multiplier 17, and this output is added with the output of multiplier 13 through adder 18 to obtain output is added with the output of multiplier 13 through adder 18 to obtain output -KA0X0+A1X1=B. On the other hand, the output of multiplier 15 is added with the output of multiplier 16 at adder 19, and the multiplication of 2b/2 is carried out via multiplier 21 to obtain (A0X1+A1+ X0)2b/2. Accordingly, AX is obtained if the output of adder 18 and multiplier 21 are added together through adder 22.
COPYRIGHT: (C)1980,JPO&Japio
JP795379A 1979-01-25 1979-01-25 Digital multiplier Granted JPS5599649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP795379A JPS5599649A (en) 1979-01-25 1979-01-25 Digital multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP795379A JPS5599649A (en) 1979-01-25 1979-01-25 Digital multiplier

Publications (2)

Publication Number Publication Date
JPS5599649A true JPS5599649A (en) 1980-07-29
JPS6122328B2 JPS6122328B2 (en) 1986-05-31

Family

ID=11679845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP795379A Granted JPS5599649A (en) 1979-01-25 1979-01-25 Digital multiplier

Country Status (1)

Country Link
JP (1) JPS5599649A (en)

Also Published As

Publication number Publication date
JPS6122328B2 (en) 1986-05-31

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