JPS55102034A - Set unit for unit address - Google Patents

Set unit for unit address

Info

Publication number
JPS55102034A
JPS55102034A JP831779A JP831779A JPS55102034A JP S55102034 A JPS55102034 A JP S55102034A JP 831779 A JP831779 A JP 831779A JP 831779 A JP831779 A JP 831779A JP S55102034 A JPS55102034 A JP S55102034A
Authority
JP
Japan
Prior art keywords
unit
address
code
fed
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP831779A
Other languages
Japanese (ja)
Inventor
Kozo Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP831779A priority Critical patent/JPS55102034A/en
Publication of JPS55102034A publication Critical patent/JPS55102034A/en
Pending legal-status Critical Current

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  • Memory System (AREA)

Abstract

PURPOSE: To simplify the address set operation and to reduce the set error, by setting the head address code with the head address set unit and the addition numeral code with the addition numeral value set unit.
CONSTITUTION: The unit address at the head given to the memory unit M1 is set in digital code by using the switches S1WS3, in the head address set unit 4. Further, a given addition numeral is set in digital code with the addition number set unit 5. The memory units M2WMn are respectively provided with the adders 62W6n, and the output of the unit 5 is fed to the first input terminal. As soon as the ouptut of the adder 6i is fed to the second input terminal of the adder 6i(where i=3Wn), the output of the adders 62W6n is fed to each comparison circuit 3 as the address code of the units M2WMn. The code set with the unit 4 is fed to the adder 62 and the unit M1. Accordingly, in the units M1WMn, the code from the unit 5 and the address code from the memory unit of the address before by one are added and it is obtained as the address code of the memory unit, allowing to simplify the address set operation.
COPYRIGHT: (C)1980,JPO&Japio
JP831779A 1979-01-26 1979-01-26 Set unit for unit address Pending JPS55102034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP831779A JPS55102034A (en) 1979-01-26 1979-01-26 Set unit for unit address

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP831779A JPS55102034A (en) 1979-01-26 1979-01-26 Set unit for unit address

Publications (1)

Publication Number Publication Date
JPS55102034A true JPS55102034A (en) 1980-08-04

Family

ID=11689769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP831779A Pending JPS55102034A (en) 1979-01-26 1979-01-26 Set unit for unit address

Country Status (1)

Country Link
JP (1) JPS55102034A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5969825A (en) * 1982-10-15 1984-04-20 Matsushita Electric Works Ltd Method for setting address of input and output device
JPS62103747A (en) * 1985-10-30 1987-05-14 Asahi Optical Co Ltd Selecting method for terminal equipment
JPS62151961A (en) * 1985-12-25 1987-07-06 Fuji Electric Co Ltd Programmable controller system
JPS6374188A (en) * 1986-09-18 1988-04-04 Canon Inc Functional block selecting device
JPH08328993A (en) * 1995-06-02 1996-12-13 Nec Corp Method and system for automatically recognizing system configuration for building block
JP2015043244A (en) * 2006-05-23 2015-03-05 コンバーサント・インテレクチュアル・プロパティ・マネジメント・インコーポレイテッドＣｏｎｖｅｒｓａｎｔ Ｉｎｔｅｌｌｅｃｔｕａｌ Ｐｒｏｐｅｒｔｙ Ｍａｎａｇｅｍｅｎｔ Ｉｎｃ． Device and method for establishing device identifier for serially interconnected device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5969825A (en) * 1982-10-15 1984-04-20 Matsushita Electric Works Ltd Method for setting address of input and output device
JPS62103747A (en) * 1985-10-30 1987-05-14 Asahi Optical Co Ltd Selecting method for terminal equipment
JPS62151961A (en) * 1985-12-25 1987-07-06 Fuji Electric Co Ltd Programmable controller system
JPH0582616B2 (en) * 1985-12-25 1993-11-19 Fuji Electric Co Ltd
JPS6374188A (en) * 1986-09-18 1988-04-04 Canon Inc Functional block selecting device
JPH08328993A (en) * 1995-06-02 1996-12-13 Nec Corp Method and system for automatically recognizing system configuration for building block
JP2015043244A (en) * 2006-05-23 2015-03-05 コンバーサント・インテレクチュアル・プロパティ・マネジメント・インコーポレイテッドＣｏｎｖｅｒｓａｎｔ Ｉｎｔｅｌｌｅｃｔｕａｌ Ｐｒｏｐｅｒｔｙ Ｍａｎａｇｅｍｅｎｔ Ｉｎｃ． Device and method for establishing device identifier for serially interconnected device

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