JPS6473814A - Clock width variation circuit - Google Patents

Abstract

PURPOSE:To easily change the duty factor of an input clock with simple circuit constitution, by taking the AND and the OR of the input clock and a delay clock in which the input clock is delayed, and selecting its output appropriately. CONSTITUTION:In case of setting a variable delay line 10a at a delay value, for example, (td), the input clock 1 inputted with the duty factor of 5% is outputted as the delay clock 2 delayed by (td). The delay clock 2 is sent as a signal 4 after the AND with the input clock 1 is taken at an AND circuit 21, and is sent as a signal 5 after the OR with the input clock 1 is taken at an OR circuit 22. In the signal 4, the duty factor is decreased as increasing the delay value (td), on the other hand, in the signal 5, the duty factor is increased as increasing the delay value (td). Next, by opening a switch SW in a selection state setting part 40a, the signal 4 is selected, and is sent as an output clock 3, and by closing the switch SW, the signal 5 is selected, and is sent as an output clock 3.