JPS6480105A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6480105A
JPS6480105A JP62238110A JP23811087A JPS6480105A JP S6480105 A JPS6480105 A JP S6480105A JP 62238110 A JP62238110 A JP 62238110A JP 23811087 A JP23811087 A JP 23811087A JP S6480105 A JPS6480105 A JP S6480105A
Authority
JP
Japan
Prior art keywords
circuit
timer counter
time
generating circuit
clock input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62238110A
Other languages
Japanese (ja)
Inventor
Takashi Harada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62238110A priority Critical patent/JPS6480105A/en
Publication of JPS6480105A publication Critical patent/JPS6480105A/en
Pending legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Oscillators With Electromechanical Resonators (AREA)

Abstract

PURPOSE:To obtain a clock generating circuit of low current consumption by providing a counter detecting a pulse width of a clock input and a cut-off circuit of a feedback resistor on a clock generating circuit. CONSTITUTION:The titled circuit acts like a conventional clock generating circuit in normal oscillation. When the pulse width of a clock input fed to an external terminal 1 is unchanged for a prescribed time, a timer counter 9 is operated. That is, when a prescribed time td is set to the timer counter 9 in advance, when the time till the output edge of the oscillation circuit 4 is changed is unchanged for the set time td or over, the timer counter 9 outputs a high level. A transmission gate T.G.10 is turned off by the output signal to cut off the feedback resistor. Then the gate T.G.10 keeps the off-state till a pulse having a width shorter than the set time td is applied to the clock input and a through-current as observed in a conventional circuit does not flow during the period.
JP62238110A 1987-09-22 1987-09-22 Semiconductor integrated circuit Pending JPS6480105A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62238110A JPS6480105A (en) 1987-09-22 1987-09-22 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62238110A JPS6480105A (en) 1987-09-22 1987-09-22 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6480105A true JPS6480105A (en) 1989-03-27

Family

ID=17025325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62238110A Pending JPS6480105A (en) 1987-09-22 1987-09-22 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6480105A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6853240B2 (en) 2002-05-24 2005-02-08 Oki Electric Industry Co., Ltd. Master clock input circuit
JP2010171685A (en) * 2009-01-22 2010-08-05 Fuji Electric Systems Co Ltd Clock synchronization circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6853240B2 (en) 2002-05-24 2005-02-08 Oki Electric Industry Co., Ltd. Master clock input circuit
JP2010171685A (en) * 2009-01-22 2010-08-05 Fuji Electric Systems Co Ltd Clock synchronization circuit

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