JPS6462914A - Clock pulse regeneration circuit - Google Patents

Clock pulse regeneration circuit

Info

Publication number
JPS6462914A
JPS6462914A JP22091987A JP22091987A JPS6462914A JP S6462914 A JPS6462914 A JP S6462914A JP 22091987 A JP22091987 A JP 22091987A JP 22091987 A JP22091987 A JP 22091987A JP S6462914 A JPS6462914 A JP S6462914A
Authority
JP
Japan
Prior art keywords
pulse
duty
flip
flop
optional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22091987A
Other languages
Japanese (ja)
Inventor
Junichi Kumada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22091987A priority Critical patent/JPS6462914A/en
Publication of JPS6462914A publication Critical patent/JPS6462914A/en
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)

Abstract

PURPOSE:To generate a pulse with an optional duty by giving an output of a differentiation circuit outputting a leading or trailing change point as a trigger pulse in an input pulse whose duty is not 50% to a flip-flop circuit as a signal as it is and retarded by a prescribed time. CONSTITUTION:The change point of the leading or trailing of a pulse signal whose duty is not 50% inputted from an input terminal 4 is differentiated by a differentiation circuit 1 to generate a trigger pulse. The generated pulse is given to a set terminal S of the flip-flop 3. On the other hand, the trigger pulse is retarded by an optional time at a delay circuit 2 and fed to a reset terminal R of the flip-flop 3. Thus, the pulse with an optional duty is generated from the output terminal 5. Even when the duty of input pulse differs, the pulse with a constant phase is outputted.
JP22091987A 1987-09-03 1987-09-03 Clock pulse regeneration circuit Pending JPS6462914A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22091987A JPS6462914A (en) 1987-09-03 1987-09-03 Clock pulse regeneration circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22091987A JPS6462914A (en) 1987-09-03 1987-09-03 Clock pulse regeneration circuit

Publications (1)

Publication Number Publication Date
JPS6462914A true JPS6462914A (en) 1989-03-09

Family

ID=16758598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22091987A Pending JPS6462914A (en) 1987-09-03 1987-09-03 Clock pulse regeneration circuit

Country Status (1)

Country Link
JP (1) JPS6462914A (en)

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