JPS647235A - In-circuit emulator - Google Patents

In-circuit emulator

Info

Publication number
JPS647235A
JPS647235A JP62162924A JP16292487A JPS647235A JP S647235 A JPS647235 A JP S647235A JP 62162924 A JP62162924 A JP 62162924A JP 16292487 A JP16292487 A JP 16292487A JP S647235 A JPS647235 A JP S647235A
Authority
JP
Japan
Prior art keywords
bus
target cpu
memory
cpu
address bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62162924A
Other languages
Japanese (ja)
Inventor
Yoshifumi Imazu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anritsu Corp
Original Assignee
Anritsu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anritsu Corp filed Critical Anritsu Corp
Priority to JP62162924A priority Critical patent/JPS647235A/en
Publication of JPS647235A publication Critical patent/JPS647235A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To read coverage data from memory without stopping the action of a target CPU by allocating the one bus cycle of the target CPU to a control CPU for a prescribed time and for the remainder, allocating the using right to the target CPU. CONSTITUTION:A control signal (g) to execute an access to a memory in which a target CPU 21 generates is introduced to a bus arbitrating means 10 and the using right of the address bus of a coverage memory 4 is determined. For a prescribed time in respective bus cycles, the address bus of the coverage memory 4 is connected to the target CPU side and for the remaining time and while the bus is in an idle condition, the address bus is connected to a control CPU 1 side respectively. Thus, by the bus arbitrating means 10, the using right of the address bus is determined and when the using right is allocated to the control CPU side, in order to read coverage data, the action of the target CPU is not stopped.
JP62162924A 1987-06-30 1987-06-30 In-circuit emulator Pending JPS647235A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62162924A JPS647235A (en) 1987-06-30 1987-06-30 In-circuit emulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62162924A JPS647235A (en) 1987-06-30 1987-06-30 In-circuit emulator

Publications (1)

Publication Number Publication Date
JPS647235A true JPS647235A (en) 1989-01-11

Family

ID=15763823

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62162924A Pending JPS647235A (en) 1987-06-30 1987-06-30 In-circuit emulator

Country Status (1)

Country Link
JP (1) JPS647235A (en)

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