JPS647148A - Processor - Google Patents

Processor

Info

Publication number
JPS647148A
JPS647148A JP16276187A JP16276187A JPS647148A JP S647148 A JPS647148 A JP S647148A JP 16276187 A JP16276187 A JP 16276187A JP 16276187 A JP16276187 A JP 16276187A JP S647148 A JPS647148 A JP S647148A
Authority
JP
Japan
Prior art keywords
data
bus
instruction
processor
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16276187A
Other languages
Japanese (ja)
Inventor
Katsuyuki Kaneko
Yuji Tanigawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP16276187A priority Critical patent/JPS647148A/en
Publication of JPS647148A publication Critical patent/JPS647148A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE:To reduce the number of parts, the number of wirings, and the number of terminals in a microprocessor and to compactly constitute a system by providing a means which temporarily stops an instruction to connect an external instruction bus and an external data bus. CONSTITUTION:A data processor 20 starts an instruction bus controller 31 and fetches an instruction through an instruction bus 22 to execute the instruction. If data is required as the result, data is accessed through a data bus 23. When a data bus access signal is inputted, a timing controller 32 temporarily stops the operation of the data processor 20. An instruction bus controller 31 disconnects an external instruction bus 26 and an internal data bus 28 from each other, and a data bus controller 30 disconnects data busses 27 and 29 from each other, and they are held if an input/output request is issued from the processor 20. Thus, the data bus 23 is accessed through the instruction bus 22.
JP16276187A 1987-06-30 1987-06-30 Processor Pending JPS647148A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16276187A JPS647148A (en) 1987-06-30 1987-06-30 Processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16276187A JPS647148A (en) 1987-06-30 1987-06-30 Processor

Publications (1)

Publication Number Publication Date
JPS647148A true JPS647148A (en) 1989-01-11

Family

ID=15760725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16276187A Pending JPS647148A (en) 1987-06-30 1987-06-30 Processor

Country Status (1)

Country Link
JP (1) JPS647148A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100399402C (en) * 2004-09-14 2008-07-02 友达光电股份有限公司 Time sequence controller with external transmission interface and electronic product using said controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100399402C (en) * 2004-09-14 2008-07-02 友达光电股份有限公司 Time sequence controller with external transmission interface and electronic product using said controller

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