JPS6433659A - Bus timing control system - Google Patents

Bus timing control system

Info

Publication number
JPS6433659A
JPS6433659A JP19088087A JP19088087A JPS6433659A JP S6433659 A JPS6433659 A JP S6433659A JP 19088087 A JP19088087 A JP 19088087A JP 19088087 A JP19088087 A JP 19088087A JP S6433659 A JPS6433659 A JP S6433659A
Authority
JP
Japan
Prior art keywords
option device
cpu
output
given
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19088087A
Other languages
Japanese (ja)
Inventor
Kenji Hibi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP19088087A priority Critical patent/JPS6433659A/en
Publication of JPS6433659A publication Critical patent/JPS6433659A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Abstract

PURPOSE:To realize the connection of an option device for a slow system with no deterioration of the CPU processing speed, by performing the wait signal control and also the thinning of the CPU clocks so as to secure the coincidence of timing between a bus signal and the option device. CONSTITUTION:The valid decoding output is delivered from a decoder 15 after detecting that an access address 13 delivered from a CPU 11 instructs an access to be given to an option device. Then the output of a signal NAND gate 22 is produced from the rise of the output of the decoder 15 by the flip-flops 17 and 18 and the gate 22. This output signal is supplied to an AND gate 24 and therefore the CPU clocks are thinned by an amount equal to a cycle. Then the CPU clocks are thinned twice when the accesses are given continuously to the option device. Thus the exactly same timing is secured for bus signals of the commands, data, etc., to be given to the option device. As a result, the option device developed for a slow system can be connected directly to a fast system for application.
JP19088087A 1987-07-30 1987-07-30 Bus timing control system Pending JPS6433659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19088087A JPS6433659A (en) 1987-07-30 1987-07-30 Bus timing control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19088087A JPS6433659A (en) 1987-07-30 1987-07-30 Bus timing control system

Publications (1)

Publication Number Publication Date
JPS6433659A true JPS6433659A (en) 1989-02-03

Family

ID=16265284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19088087A Pending JPS6433659A (en) 1987-07-30 1987-07-30 Bus timing control system

Country Status (1)

Country Link
JP (1) JPS6433659A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04233059A (en) * 1990-06-25 1992-08-21 Internatl Business Mach Corp <Ibm> Information processing apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04233059A (en) * 1990-06-25 1992-08-21 Internatl Business Mach Corp <Ibm> Information processing apparatus

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