JPS6468865A - Bus connection arbitrating system - Google Patents

Bus connection arbitrating system

Info

Publication number
JPS6468865A
JPS6468865A JP22710087A JP22710087A JPS6468865A JP S6468865 A JPS6468865 A JP S6468865A JP 22710087 A JP22710087 A JP 22710087A JP 22710087 A JP22710087 A JP 22710087A JP S6468865 A JPS6468865 A JP S6468865A
Authority
JP
Japan
Prior art keywords
request
bus cycle
priority level
processor
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22710087A
Other languages
Japanese (ja)
Inventor
Yoshiaki Igarashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22710087A priority Critical patent/JPS6468865A/en
Publication of JPS6468865A publication Critical patent/JPS6468865A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To eliminate the load of a program by giving priority levels to use request at the time of collision between them and reporting bus cycle error to a requester whose request has the lower priority level and preferentially processing the request having the higher priority level. CONSTITUTION:When the operation request of a local memory MEM1 occurs in a processor CPU 2, a bus connection arbitrating system CONAB1 receives requests from a processor CPU1 and the processor CPU2 and acknowledges the request having the higher priority level by the judgement of precedence circuit in the bus connection arbitrating system CONAB1 and outputs the bus cycle error report to the requester whose request has the lower priority level. The processor CPU2 which receives the bus cycle error report judges that error occurs in the current bus cycle execution, and the processor CPU2 interrupts the bus cycle to start the bus cycle error processing. Thus, the program processing of microprocessors for these operations is eliminated.
JP22710087A 1987-09-10 1987-09-10 Bus connection arbitrating system Pending JPS6468865A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22710087A JPS6468865A (en) 1987-09-10 1987-09-10 Bus connection arbitrating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22710087A JPS6468865A (en) 1987-09-10 1987-09-10 Bus connection arbitrating system

Publications (1)

Publication Number Publication Date
JPS6468865A true JPS6468865A (en) 1989-03-14

Family

ID=16855486

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22710087A Pending JPS6468865A (en) 1987-09-10 1987-09-10 Bus connection arbitrating system

Country Status (1)

Country Link
JP (1) JPS6468865A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03271855A (en) * 1990-03-20 1991-12-03 Hitachi Ltd Bus control system, information processing system, and bus controller
JP2001109723A (en) * 1999-08-21 2001-04-20 Koninkl Philips Electronics Nv Multiprocessor system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03271855A (en) * 1990-03-20 1991-12-03 Hitachi Ltd Bus control system, information processing system, and bus controller
JP2001109723A (en) * 1999-08-21 2001-04-20 Koninkl Philips Electronics Nv Multiprocessor system

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