JPS6460109A - Cmos input buffer circuit - Google Patents

Cmos input buffer circuit

Info

Publication number
JPS6460109A
JPS6460109A JP62217506A JP21750687A JPS6460109A JP S6460109 A JPS6460109 A JP S6460109A JP 62217506 A JP62217506 A JP 62217506A JP 21750687 A JP21750687 A JP 21750687A JP S6460109 A JPS6460109 A JP S6460109A
Authority
JP
Japan
Prior art keywords
circuit
cmos
ttl
channel
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62217506A
Other languages
Japanese (ja)
Inventor
Hideki Shudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62217506A priority Critical patent/JPS6460109A/en
Publication of JPS6460109A publication Critical patent/JPS6460109A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable

Abstract

PURPOSE:To attain connection to a TTL (transistor transistor logic) circuit and to a CMOS circuit with one circuit by inserting the source of the two numbers of transistors of a P channel and the drain switch means of the transistor of an N channel and executing on and off operation with a control signal. CONSTITUTION:A switch means 900 is inserted between the two numbers of transistors 700 and 800 of the P channel and the drain of transistors 500 and 600 of the N channel. When the output of the TTL is connected to the input of a CMOS input buffer circuit, since the switch means 900 is turned off by the control signal and a threshold to identify an H level is lowered, an interface with the TTL can be obtained. On the other hand, when the other output of the other CMOS is connected to the input of the CMOS buffer circuit, the switch means 900 is turned off by the control signal and without lowering the threshold to identify the H level, the interface with the other CMOS can be obtained. Thus, the connection can be executed to the TTL circuit and the CMOS circuit by the control signal with one circuit.
JP62217506A 1987-08-31 1987-08-31 Cmos input buffer circuit Pending JPS6460109A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62217506A JPS6460109A (en) 1987-08-31 1987-08-31 Cmos input buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62217506A JPS6460109A (en) 1987-08-31 1987-08-31 Cmos input buffer circuit

Publications (1)

Publication Number Publication Date
JPS6460109A true JPS6460109A (en) 1989-03-07

Family

ID=16705301

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62217506A Pending JPS6460109A (en) 1987-08-31 1987-08-31 Cmos input buffer circuit

Country Status (1)

Country Link
JP (1) JPS6460109A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0405833A2 (en) * 1989-06-30 1991-01-02 AT&T Corp. Programmable logic level input buffer
JPH03132211A (en) * 1989-09-12 1991-06-05 Samsung Semiconductor Inc Ttl/cmos level converter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0405833A2 (en) * 1989-06-30 1991-01-02 AT&T Corp. Programmable logic level input buffer
JPH0338873A (en) * 1989-06-30 1991-02-19 American Teleph & Telegr Co <Att> Integrated circuit
EP0405833A3 (en) * 1989-06-30 1991-11-06 American Telephone And Telegraph Company Programmable logic level input buffer
JPH03132211A (en) * 1989-09-12 1991-06-05 Samsung Semiconductor Inc Ttl/cmos level converter

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