JPS6481412A - Input buffer circuit - Google Patents

Input buffer circuit

Info

Publication number
JPS6481412A
JPS6481412A JP62237232A JP23723287A JPS6481412A JP S6481412 A JPS6481412 A JP S6481412A JP 62237232 A JP62237232 A JP 62237232A JP 23723287 A JP23723287 A JP 23723287A JP S6481412 A JPS6481412 A JP S6481412A
Authority
JP
Japan
Prior art keywords
buffer circuit
input buffer
switch
switch element
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62237232A
Other languages
Japanese (ja)
Inventor
Takao Naito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP62237232A priority Critical patent/JPS6481412A/en
Publication of JPS6481412A publication Critical patent/JPS6481412A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To set the level of an output signal to '1' or '0' selectively by selecting the switch states of a 1st or 2nd switch element unless a normal signal is supplied to the input terminal of an input buffer circuit. CONSTITUTION:A pull-up resistance Rpu is couple with an input signal line SL connecting to an amplifying circuit through the 1st switch element Q3 and a pull-down resistance Rpa is coupled through the 2nd switch element Q4 to control the 1st and 2nd switch elements Q3 and Q4 complementarily. Consequently, when a normal signal whose logical level is determined is not supplied to the external input terminal Pi of the input buffer circuit, the output signal level of the input buffer circuit is set selectively and optionally to either logic '1' or '0' according to the switch states of selection MOSFETs Q3 and Q4.
JP62237232A 1987-09-24 1987-09-24 Input buffer circuit Pending JPS6481412A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62237232A JPS6481412A (en) 1987-09-24 1987-09-24 Input buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62237232A JPS6481412A (en) 1987-09-24 1987-09-24 Input buffer circuit

Publications (1)

Publication Number Publication Date
JPS6481412A true JPS6481412A (en) 1989-03-27

Family

ID=17012342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62237232A Pending JPS6481412A (en) 1987-09-24 1987-09-24 Input buffer circuit

Country Status (1)

Country Link
JP (1) JPS6481412A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03212021A (en) * 1990-01-17 1991-09-17 Matsushita Electric Ind Co Ltd Input buffer circuit
JPH04266217A (en) * 1991-02-21 1992-09-22 Matsushita Electric Ind Co Ltd Input buffer circuit
JP2011207142A (en) * 2010-03-30 2011-10-20 Brother Industries Ltd Control circuit, controller, control method, and image forming apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03212021A (en) * 1990-01-17 1991-09-17 Matsushita Electric Ind Co Ltd Input buffer circuit
JPH04266217A (en) * 1991-02-21 1992-09-22 Matsushita Electric Ind Co Ltd Input buffer circuit
JP2011207142A (en) * 2010-03-30 2011-10-20 Brother Industries Ltd Control circuit, controller, control method, and image forming apparatus
US8334711B2 (en) 2010-03-30 2012-12-18 Brother Kogyo Kabushiki Kaisha Control circuit, control device, control method, and image forming apparatus

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