JPS6482384A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6482384A
JPS6482384A JP62237148A JP23714887A JPS6482384A JP S6482384 A JPS6482384 A JP S6482384A JP 62237148 A JP62237148 A JP 62237148A JP 23714887 A JP23714887 A JP 23714887A JP S6482384 A JPS6482384 A JP S6482384A
Authority
JP
Japan
Prior art keywords
level
bipolar
axi
attain
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62237148A
Other languages
Japanese (ja)
Inventor
Kayoko Kono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62237148A priority Critical patent/JPS6482384A/en
Publication of JPS6482384A publication Critical patent/JPS6482384A/en
Pending legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To shorten the transfer delay time of an input signal by a level decision circuit and to attain a high speed access time by controlling the reference potential of a bipolar current switch circuit according to the level of the input signal. CONSTITUTION:For instance, in a bipolar CMOS type RAM, the bipolar current switch circuit constituting the level decision circuit of an X address buffer XADB is formed to be a VTL (Variable Threshold Logic) circuit formation to control gradually the reference potential according to the level of corresponding X address signals AXO-AXi. Thereby, the transfer delay time of the X address signals AXO-AXi in the X address buffer XADB is reduced to attain the high speed of the bipolar CMOS type RAM.
JP62237148A 1987-09-24 1987-09-24 Semiconductor integrated circuit device Pending JPS6482384A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62237148A JPS6482384A (en) 1987-09-24 1987-09-24 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62237148A JPS6482384A (en) 1987-09-24 1987-09-24 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6482384A true JPS6482384A (en) 1989-03-28

Family

ID=17011116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62237148A Pending JPS6482384A (en) 1987-09-24 1987-09-24 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6482384A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03144997A (en) * 1989-10-30 1991-06-20 Internatl Business Mach Corp <Ibm> Memory and bit decoder circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03144997A (en) * 1989-10-30 1991-06-20 Internatl Business Mach Corp <Ibm> Memory and bit decoder circuit

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