JPS645462B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a semiconductor integrated circuit device.

In recent years, in order to improve the degree of integration of semiconductor integrated circuit devices, a so-called "groove element isolation method" in which a groove is dug in an isolation region has been attracting attention. The method shown in FIG. 1 involves growing a silicon oxide film 103 and a silicon nitride film 104 on a silicon substrate 101, digging a trench 102, growing a silicon nitride film again, and using an anisotropic dry etching method. Nitride film 10 on the side surface of the groove
4 (FIG. 1A), the selective oxidation method realizes a small lateral encroachment, that is, a small pattern conversion difference, and a high field reversal voltage (FIG. 1B). However, this method has the disadvantage that stress is applied to the substrate during oxidation, thereby introducing crystal defects and inducing deterioration of characteristics. Also the second
In the method shown in the figure, a polycrystalline silicon film 202 is grown to a sufficient thickness (second
By using a smoothing method in combination with a dry etching method on the entire surface after applying a photoresist as shown in FIG. A), a flat element isolation method with fewer introduced defects is realized as shown in FIG. 2B. However, this method has the disadvantage that it is difficult to obtain a high field inversion voltage.

An object of the present invention is to provide a highly reliable semiconductor integrated circuit device that has a high field reversal voltage, has few crystal defects, and has excellent characteristics by using a trench isolation method. be.

A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device using a trench digging element isolation method, in which a first silicon oxide film grown on the bottom of a trench forms a second silicon oxide film grown on a side surface of the trench. It is thicker than the oxide film and insufficiently thick to fill the steps in the trench, and the remaining steps are filled with a polycrystalline silicon film.
an element isolation region provided with a diffusion layer for preventing field inversion through a silicon oxide film, and an element isolation region having a conductivity type opposite to that of the semiconductor base through a second silicon oxide film to the semiconductor base on the side surface of the trench. an impurity diffusion layer is provided, the polycrystalline silicon for trench filling has sufficient impurities introduced to form an electrode, and is connected to a constant potential, and the polycrystalline silicon for trench filling is The present invention is characterized in that a side surface of the trench facing the impurity diffusion layer is used as a part of a capacitor of the memory element.

Since the device according to the present invention only partially fills the trench with a silicon oxide film, excessive stress is not applied to the semiconductor substrate, and the introduction of crystal defects can be minimized. Furthermore, by optimizing the thickness of the silicon oxide film at the bottom of the trench and forming an impurity diffusion layer for preventing field inversion, a sufficiently high field inversion voltage can be achieved. The stepped portions that are not filled with the silicon oxide film are filled with the polycrystalline silicon film and can be sufficiently smoothed, so that reliability problems such as wiring breaks can be virtually eliminated.

In addition, by using a polycrystalline silicon film as an electrode connected to a constant potential and utilizing the difference in the thickness of the silicon oxide film grown on the bottom and side surfaces of the trench, the area of the capacitor part of the 1-transistor/cell type is increased. This makes it possible to achieve high integration of dynamic MOS memory.

Next, embodiments of the present invention will be described using the drawings.

FIG. 3 is a cross-sectional view of the element isolation part of the first reference example of the present invention, in which the bottom of a groove dug to a depth of 2 microns on a silicon substrate 301 has a depth of 0.5 microns.
A micron silicon oxide film 303 is formed, and a 500 Å silicon oxide film 302 is grown on the sides of the trench and in areas other than the trench portion. The 1.7 micron step difference left by the groove is filled with the polycrystalline silicon film 304, and isolation between elements with almost negligible step difference can be achieved without introducing defects into the substrate.

Further, in a second reference example related to the present invention shown in FIG. 4, a thick silicon oxide film 403 at the bottom of the trench is
When P-type silicon is used, a p-type impurity diffusion layer 404 is formed in the silicon substrate portion in contact with the polycrystalline silicon film 405 used for embedding. Since phosphorus is added to the wires and the wires are connected to 0V potential, extremely stable isolation between elements can be achieved.

FIG. 5 shows an embodiment of the present invention, in which a one-transistor/cell type dynamic MOS memory is constructed using the element isolation method according to the present invention. A trench is formed on a P-type silicon substrate 501, and a 0.5 micron field oxide film 50 is formed at the bottom of the trench.
3 and a p-type impurity diffusion layer 504 for preventing field inversion, the field inversion voltage is 30 V or more, allowing stable isolation between elements. A silicon oxide film 502 with a thickness of 200 Å is grown on the side surfaces of the trench, forming part of the cell capacitance. The counter electrode of the cell capacitor is an n-type impurity diffusion layer 50
5 and a trench-filling polycrystalline silicon film 506. The other cell configurations are the same as the normal one-transistor/cell type, with the second polycrystalline silicon film 508 forming the transfer gate, and the aluminum wiring 511 forming the bit line. According to this invention, since the groove side surface can be used as a part of the cell capacity, a three-dimensional capacitor configuration is possible, and 256K bits or 1M bits can be realized.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are explanatory diagrams of the conventional trench isolation method, in which 101 is a silicon substrate, 102 is a trench, 103 is a silicon oxide film, 104 is a silicon nitride film, and 105 is silicon for filling the trench. Oxide film, 20
1 is a silicon substrate, 202 is a groove, 203 is a silicon oxide film, 204 is a polycrystalline silicon film for filling the groove,
It is. 3 and 4 are reference examples of the device isolation method related to the present invention, respectively, in which 301 is a silicon substrate, 302 is a thin silicon oxide film on the side surfaces of the trench, 303 is a thick silicon oxide film on the bottom of the trench, and 304
4 is a polycrystalline silicon film for filling the trench, 401 is a silicon substrate, 402 is a thin silicon oxide film on the side surface of the trench, 4
03 is a thick silicon oxide film at the bottom of the trench, 404 is an impurity diffusion layer for preventing field inversion, and 405 is a polycrystalline silicon film for filling the trench. FIG. 5 shows an embodiment in which the present invention is applied to a one-transistor/cell type dynamic MOS memory, in which 501 is a p-type silicon substrate, 502 is a capacitance gate silicon oxide film on the side surface of the trench, and 503 is a field silicon oxide film on the bottom of the trench. , 504 is a p-type diffusion layer for preventing field inversion, 506 is a trench-filling polycrystalline silicon film serving as a capacitor electrode, 508 is a transfer gate second polycrystalline silicon electrode, and 511 is an aluminum bit line.

Claims (1)

[Claims] 1 In a semiconductor integrated circuit device using the trench trench isolation method, the first silicon oxide film grown on the bottom of the trench is thicker than the second silicon oxide film grown on the side surfaces of the trench, and The film thickness is insufficient to fill the step, and the remaining step is filled with a polycrystalline silicon film, and the semiconductor substrate at the bottom of the trench is diffused to prevent field reversal through the first silicon oxide film. an element isolation region comprising a layer;
An impurity diffusion layer of a conductivity type opposite to that of the semiconductor substrate is provided on the semiconductor substrate on the side surface of the groove via the second silicon oxide film, and the polycrystalline silicon for filling the groove is used to form an electrode. A portion of the capacitive portion of the memory element is connected to a side surface of the trench in which sufficient impurities are introduced and connected to a constant potential, and the trench-filling polycrystalline silicon film and the impurity diffusion layer face each other. A semiconductor integrated circuit device characterized in that it is used as a semiconductor integrated circuit device.