JP3018017B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] An element or a part of an element is selectively formed on a lower surface, and an element or a part of an element is selectively formed on an upper surface in alignment with the lower surface. A second semiconductor substrate, in which a trench penetrating through is formed selectively, and a part of the element is formed on a part of the side surface of the trench, is bonded to the first semiconductor substrate via a first insulating film. In this structure, a part of the element (charge storage electrode) can be selectively formed on the upper surface, the lower surface, and the side surface of the second semiconductor substrate, and the lower surface and the second surface of the second semiconductor substrate can be selectively formed. In order to achieve high integration by forming a part of a device (cell plate electrode) via an insulating film on a part of a side surface of a trench selectively formed in a semiconductor substrate, a counter electrode having a large area is formed. And increase the capacitor capacity It is possible to improve the α ray soft errors by Rukoto.
In addition, an element can be easily formed on the insulating film by combining the island-like isolation of the element with the insulating film, and a so-called SOI structure element can be formed on a silicon substrate without using recrystallized silicon. , And the speed can be increased by reducing the bit line junction capacitance.

That is, a semiconductor device capable of forming an extremely high-performance and highly integrated semiconductor integrated circuit is provided.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MIS type semiconductor device, and more particularly, to a semiconductor device which realizes formation of an element having an SOI structure on a silicon substrate and enables formation of an extremely high performance and highly integrated semiconductor integrated circuit. .

Conventionally, in the formation of a dynamic random access memory (DRAM) composed of one transistor and one capacitor, a trench-structured capacitor is used in order to secure a sufficient capacitance of the capacitor. In recent years, it is difficult to form a fine and deep trench, it is difficult to grow a uniform thin insulating film in the deep trench, and it is difficult to embed a polycrystalline silicon layer serving as a cell plate electrode in the deep trench. And other problems in manufacturing technology have become remarkable. Therefore, in order to obtain a highly integrated semiconductor integrated circuit, there is a demand for the development of a semiconductor device having a small occupied area and a structure capable of sufficiently securing a capacitor capacity.

[Prior Art] FIG. 3 is a schematic side sectional view of a conventional semiconductor device, and shows a DRAM memory cell having a trench capacitor. 51 is a p ^- type silicon (Si) substrate, 52 is a p-type well region, 53 is a p ⁺ -type impurity region, 54 is an n ⁺ -type impurity region (charge storage electrode), 55 is a field oxide film, and 56 is a capacitor insulating film. , 57 is a cell plate electrode (polycrystalline silicon), 58 is a gate oxide film, 59 is a word line (polycrystalline silicon),
60 is a block oxide film, 61 is a phosphosilicate glass (PSG), 62
Indicates a bit line (Al wiring).

In the figure, a p ^- type silicon substrate substrate 51 is selectively provided with a p-type well region 52, and a memory cell including a trench capacitor and a transfer gate is formed in the p-type well region 52. The trench-type capacitor has a charge storage electrode 54 made of an n ⁺ -type impurity region on the side and bottom of the trench, and a cell plate electrode 57 made of polycrystalline silicon embedded in the trench via a capacitor insulating film 56 as two electrodes. A high-concentration p ⁺ -type impurity region 53 is in contact with the n ⁺ -type impurity region 54 to form a capacitor having a so-called HiC structure. Here, adjacent trench type capacitors are separated and defined by the field oxide film 55. In order to improve the soft error due to α-rays, it is necessary to increase the capacitance of the capacitor.However, it is difficult to form a deep trench to secure a sufficient capacitance, It is difficult to grow a thin film capacitor insulating film and there is a problem in manufacturing technology such as difficulty in adhesion of polycrystalline silicon filling deep trenches. There is a disadvantage that a trench capacitor cannot be formed.

[Problems to be Solved by the Invention] The problem to be solved by the present invention is that, as shown in the conventional example, a trench-type capacitor theoretically requires a fine opening area if a deep trench is formed. Although it should be possible to secure a large capacitance, it is difficult to form a deep trench perpendicular to the bottom, and a thin film capacitor insulating film with a uniform thickness is grown on the side wall and bottom of the deep trench. It is difficult to form a capacitor having sufficient capacitance with a finer opening area because it is difficult to make the conductive film for the electrode in the deep trench with good adhesion to the underlying insulating film. is there.

[Means for Solving the Problem] The above problem is a semiconductor device in which a second semiconductor substrate is bonded to a first semiconductor substrate with a first insulating film interposed therebetween. An impurity region of a conductivity type opposite to the second semiconductor substrate selectively formed on the lower surface of the second semiconductor substrate; and an impurity region opposite to the second semiconductor substrate selectively formed on the upper surface of the second semiconductor substrate. A conductive type impurity region and an impurity region of a conductivity type opposite to the second semiconductor substrate formed on a part of a side surface of a trench selectively penetrating from an upper surface to a lower surface of the second semiconductor substrate; And a first conductive film formed through a second insulating film formed on the lower surface of the second semiconductor substrate.
The second conductive film buried through the third insulating film formed on the side wall of the trench forms a cell plate electrode, and the second insulating film and the third insulating film form a capacitor insulating film. The problem is solved by a capacitor having an SOI structure formed by a bonded semiconductor substrate.

[Operation] That is, in the semiconductor device of the present invention, an element or part of an element is selectively formed on the lower surface, and the element or part of the element is selectively formed on the upper surface in alignment with the element. And a trench penetrating from the upper surface to the lower surface is selectively formed,
Further, a second semiconductor substrate in which a part of the element is formed on a part of the side surface of the trench is formed on the first semiconductor substrate with a first insulating film interposed therebetween.
Therefore, a part of the element (charge storage electrode) can be selectively formed on the upper surface, the lower surface, and the side surface of the second semiconductor substrate, and can be selectively formed on the lower surface of the second semiconductor substrate and the second semiconductor substrate. The high integration due to the formation of a part of the element (cell plate electrode) on each side surface of the trench through an insulating film can be achieved because the counter electrode having a large area can be formed and the capacitance of the capacitor can be increased. It is possible to improve the α-ray soft error, and it is also possible to easily form an element on the insulating film by combining the island-like separation of the element with the insulating film, and to use a silicon substrate instead of recrystallized silicon. Since an element with a so-called SOI structure can be formed, M
It is possible to make the characteristics of the OS field effect transistor stable and to increase the speed by reducing the bit line junction capacitance.

That is, an extremely high performance and highly integrated semiconductor integrated circuit can be obtained.

EXAMPLES Hereinafter, the present invention will be described specifically with reference to illustrated examples.

FIG. 1 is a schematic side sectional view of one embodiment of a semiconductor device of the present invention, and FIGS. 2 (a) to (e) are process sectional views of one embodiment of a method of manufacturing a semiconductor device of the present invention. The same objects are denoted by the same reference numerals throughout the drawings.

In schematic side sectional view of an embodiment Figure 1 is in the semiconductor device of the present invention when using a p-type silicon substrate 1 is 10 ¹⁵ cm
^-3 p ^- type first silicon (Si) substrate, 2 is an oxide film (first insulating film) of about 1 μm, 3 is p ^- type second silicon (Si) of about 10 ¹⁶ cm ^-3 Substrate, 16 is a gate oxide film of about 20 nm, 18 is an oxide film for impurity block of about 50 nm, 19 is 0.8
Phosphor silicate glass (PSG) film of about 1 μm, 20 is A of about 1 μm
l wiring, 27 is a sidewall insulating film (third insulating film) of about 0.1 μm, 28 is a buried conductive film (second conductive film, selective chemical vapor deposition tungsten film), 33 is a cell plate electrode of about 0.3 μm (First conductive film, polycrystalline silicon), 34 is 20 nm
Capacitor insulating film (second insulating film), 35 is 10 ²⁰ cm
^-3 charge storage electrode (n ⁺ type impurity region), 36 is 10 ²⁰ cm
^-3 bit lines (n ⁺ type impurity region), 37 is 0.3μ
A word line (gate electrode) of about m is shown.

FIG. 1 shows a main part of a DRAM memory cell having one transistor and one capacitor. p ^- type second
Silicon (Si) word line 37 on the upper surface of the substrate 3, the bit line 36, charges n ⁺ -type impurity region is provided to accumulate, the lower surface selectively n ⁺ -type impurity region is provided, p ^- -type The n ⁺ -type impurity regions provided on a part of the side surface of the trench formed in the second silicon (Si) substrate 3 make the n ⁺ -type upper and lower surfaces n ⁺
The type impurity regions are connected to form a charge storage electrode 35. On the lower surface, a cell plate electrode 33 is formed via a capacitor insulating film 34, and the cell plate electrode 33 is formed.
The connection to is made using a technique using a selective chemical vapor deposition tungsten film 28 (which also becomes a cell plate electrode). In the above embodiment, since a capacitor can be formed on the side surface and the lower surface of the p ⁻ type second silicon (Si) substrate 3, the capacitance can be greatly increased, and the α-ray soft error resistance can be improved and the integration can be increased. Becomes However, the controllability of forming the thin film of the side wall insulating film (third insulating film) 27 is a little more difficult than that of the capacitor insulating film 34 formed on the lower surface. Is smaller than the capacity formed on the lower surface.

In the semiconductor device of the present invention, alignment between an element or a part of an element selectively formed on the lower surface and an element or a part of the element selectively formed on the upper surface uses an alignment pattern formed as follows. It is done. First, a trench having a depth of about 6 μm is provided on the lower surface of the second silicon (Si) substrate, and an element or a part of the element is selectively formed on the lower surface in alignment with the trench. Embedding, then bonding the second silicon (Si) substrate to the first silicon (Si) substrate via the insulating film, then grinding the second silicon (Si) substrate to about 5 μm,
Then, by etching the insulating film exposed from the upper surface of the second silicon (Si) substrate, the trench provided on the lower surface can be formed on the upper surface by self-alignment. Alternatively, when a part of the element is formed, the element or part of the element on the upper surface can be directly aligned with the element or part of the element on the lower surface.

Next, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 2 (a) to 2 (e) and FIG. However, here, only the manufacturing method relating to the formation of the memory cells (capacitors and transistors) of the DRAM of the present invention is described, and the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit is described. The description of the manufacturing method is omitted.

FIG. 2 (a) P ^- type silicon substrate 3 is thermally oxidized to grow a thin oxide film (not shown). Next, arsenic is ion-implanted on the lower surface of the p ⁻ -type silicon substrate 3 using a resist (not shown) as a mask layer by using a normal photolithography technique, and n ⁺
The type impurity region 35 is selectively formed. Next, the resist (not shown) is removed. Next, the thin oxide film (not shown) is removed by etching.

FIG. 2 (b) Then, the p ^- type silicon substrate 3 is thermally oxidized to grow a capacitor oxide film. Next, a polycrystalline silicon film including an n ⁺ -type high-concentration impurity region is grown on capacitor oxide film. Next, the polycrystalline silicon film is thermally oxidized to form an oxide film. Next, the p ^- type silicon substrate 1 is thermally oxidized to grow an oxide film. Next, heat treatment is performed on the p ^- type silicon substrate 1
The lower surface of the p ^- type silicon substrate 3 is bonded on top. Then
The upper surface of the p ^- type silicon (Si) substrate 3 is ground to a thickness of about 5 μm.

Next, an oxide film 39 and a nitride film 40 are grown on the upper surface of the p ^- type silicon (Si) substrate 3 (FIG. 2C). Next, using a normal photolithography technique, a nitride film 40, an oxide film 39, and p ^- type silicon (S
i) The substrate 3 and the capacitor oxide film 34 are sequentially subjected to anisotropic dry etching to form a trench penetrating from the upper surface to the lower surface of the p ^- type silicon (Si) substrate 3. Next, the resist (not shown) is removed. Next, a buried element isolation region is formed in the trench with a trench buried oxide film (not shown). Next, using a resist (not shown) as a mask layer, a part of the buried oxide film (not shown) of the trench is removed by etching using a normal photolithography technique. Next, arsenic is ion-implanted into the side surface of the newly opened trench to form an n ⁺ -type impurity region 35.
Next, the resist (not shown) is removed.

FIG. 2 (d) Next, an oxide film is formed by a chemical vapor deposition method. Next, anisotropic dry etching is performed to leave the sidewall oxide film 27 on the sidewall of the trench. Next, selective chemical vapor deposition tungsten film
28 is embedded in the trench. Next, the nitride film 40 and the oxide film 39
Are sequentially removed by etching.

FIG. 2 (e) Next, the gate oxide film 16 is grown by thermal oxidation. Next, a polycrystalline silicon film containing impurities is grown. Next, the gate electrode 37 (word line) is formed by performing anisotropic dry etching of the polycrystalline silicon film using a resist (not shown) as a mask layer by using a normal photolithography technique. Next, the resist (not shown) is removed. Next, arsenic is ion-implanted using a resist (not shown), a gate electrode 37, and a trench buried oxide film (not shown) in the element isolation region as a mask layer by using a normal photolithography technique, and n ⁺ -type impurities are implanted. Define the area (35, 36). Next, the resist (not shown) is removed. Next, unnecessary portions of the gate oxide film 16 are removed by etching.

FIG. 1 Then, the growth of the impurity blocking oxide film 18 and the phosphosilicate glass (PSG) film 19 are
Activation of the impurity diffusion region by high-temperature heat treatment, control of the depth, formation of an electrode contact window, formation of an Al wiring 20, and the like are performed to complete a semiconductor device (a memory cell of a DRAM).

As described in the above embodiments, according to the semiconductor device of the present invention, a part of the element (charge storage electrode) can be selectively formed on the upper surface, the lower surface, and the side surface of the second semiconductor substrate, and The high integration due to the fact that a part of the element (cell plate electrode) can be formed via an insulating film on the lower surface of the semiconductor substrate and a part of the side surface of the trench selectively formed in the second semiconductor substrate, respectively. , The α-ray soft error can be improved by increasing the capacitance of the capacitor. In addition, an element can be easily formed on the insulating film by combining the island-like isolation of the element with the insulating film, and a so-called SOI structure element can be formed on a silicon substrate without using recrystallized silicon. , And the speed can be increased by reducing the bit line junction capacitance.

[Effects of the Invention] As described above, according to the present invention, in a MIS type semiconductor device, it is possible to form an SOI structure using a silicon substrate.
Can be formed in a structure in which the capacitance of the capacitor is sufficiently increased and the memory cell is fine, so that a highly integrated semiconductor integrated circuit having improved α-ray soft error resistance can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic side sectional view of one embodiment of a semiconductor device of the present invention, FIGS. 2 (a) to 2 (e) are cross-sectional views of steps of an embodiment of a structure method of a semiconductor device of the present invention, FIG. Is a schematic side sectional view of a conventional semiconductor device. In the figure, 1 is a p ^- type first silicon (Si) substrate, 2 is an oxide film, 3 is a p ^- type second silicon (Si) substrate, 16 is a gate oxide film, 18 is an oxide film for impurity blocking, 19 is a phosphosilicate glass (PSG) film, 20 is an Al wiring, 27 is a side wall insulating film, 28 is a buried conductive film (selective chemical vapor deposition tungsten film), 33 is a cell plate electrode, 34 is a capacitor insulating film, 35 is A charge storage electrode, 36 indicates a bit line, and 37 indicates a word line.

Claims (2)

(57) [Claims] 1. A semiconductor device in which a second semiconductor substrate is bonded to a first semiconductor substrate via a first insulating film, and is selectively formed on a lower surface of the second semiconductor substrate. Element or part of the element, and selectively formed on the upper surface of the second semiconductor substrate in accordance with the element or part of the element selectively formed on the lower surface of the second semiconductor substrate. An element or a part of the element, a trench selectively penetrating from an upper surface to a lower surface of the second semiconductor substrate, and a part of an element formed on a side surface of a part of the trench; Part of the element selectively formed on the upper and lower surfaces of the second semiconductor substrate and a part of the side surface of the trench forms a charge storage electrode, and the lower surface of the second semiconductor substrate has a second insulating film interposed therebetween. Forming a third insulating film on the first conductive film formed by None the second conductive film cell plate electrode buried in said second insulating film and the third
Wherein the insulating film forms a capacitor that forms a capacitor insulating film. 2. The method according to claim 1, wherein said second semiconductor substrate is aligned with an alignment pattern (trench) formed on a lower surface of said second semiconductor substrate.
After forming an element or a part of the element on the lower surface of the semiconductor substrate, the second semiconductor substrate is bonded to the first semiconductor substrate via an insulating film, and then the upper surface of the second semiconductor substrate is By grinding, the alignment pattern (trench) is exposed on the upper surface of the second semiconductor substrate,
Forming an element or a part of the element on the upper surface of the second semiconductor substrate by aligning with an alignment pattern (trench) exposed on the upper surface of the second semiconductor substrate. A method for manufacturing a semiconductor device.