JPS6448153A - Memory controller - Google Patents
Memory controllerInfo
- Publication number
- JPS6448153A JPS6448153A JP62205867A JP20586787A JPS6448153A JP S6448153 A JPS6448153 A JP S6448153A JP 62205867 A JP62205867 A JP 62205867A JP 20586787 A JP20586787 A JP 20586787A JP S6448153 A JPS6448153 A JP S6448153A
- Authority
- JP
- Japan
- Prior art keywords
- data
- memory
- error
- memories
- alternative
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
PURPOSE:To improve the reliability of a memory part by subjecting data, where error occurs, to one-bit correction and writing this corrected data and reading out the same data again and substituting an alternative memory for a pertinent memory element at the time of detecting hard error in this read data. CONSTITUTION:Alternative memories 211-241 are provided in a memory part 2, and a patrol control part 4 reads data from the memory part 2 and reads out corrected data after one-bit error correction in an error correction detecting circuit 5 and detects the presence or the absence of hard error. The error bit based on syndrome data and the upper address indicating the position of an IC memory where hard error is detected are stored in a syndrome storage means 6, and IC memories 21-24 are switched to alternative memories 211-241 by a data bus switching part 7 in accordance with contents of the syndrome storage means 6. Thus, the memory element where hard error occurs is substituted to improve the reliability.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62205867A JPS6448153A (en) | 1987-08-19 | 1987-08-19 | Memory controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62205867A JPS6448153A (en) | 1987-08-19 | 1987-08-19 | Memory controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6448153A true JPS6448153A (en) | 1989-02-22 |
Family
ID=16514036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62205867A Pending JPS6448153A (en) | 1987-08-19 | 1987-08-19 | Memory controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6448153A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013127820A (en) * | 2007-12-14 | 2013-06-27 | Toshiba Corp | Control device |
CN103942119A (en) * | 2013-12-26 | 2014-07-23 | 杭州华为数字技术有限公司 | Method and device for processing memory errors |
-
1987
- 1987-08-19 JP JP62205867A patent/JPS6448153A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013127820A (en) * | 2007-12-14 | 2013-06-27 | Toshiba Corp | Control device |
CN103942119A (en) * | 2013-12-26 | 2014-07-23 | 杭州华为数字技术有限公司 | Method and device for processing memory errors |
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