JPS6448064U - - Google Patents
Info
- Publication number
- JPS6448064U JPS6448064U JP14229287U JP14229287U JPS6448064U JP S6448064 U JPS6448064 U JP S6448064U JP 14229287 U JP14229287 U JP 14229287U JP 14229287 U JP14229287 U JP 14229287U JP S6448064 U JPS6448064 U JP S6448064U
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- circuit board
- via holes
- board
- identification mark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Tests Of Electronic Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Description
第１図は本考案によるプリント基板の部分平面
図、第２図は従来のプロービングテストの一方法
を示す側面図、第３図は従来の表面実装型プリン
ト基板における改造用布線によるプロービングテ
ストの妨害状況を示す側面図である。
１……リード、２……プリント基板、３……電
気部品、４……テストピン、５……改造用布線、
６……専用パツド、７……端子、８……バイアホ
ール、１０……識別標識。
Fig. 1 is a partial plan view of a printed circuit board according to the present invention, Fig. 2 is a side view showing a conventional probing test method, and Fig. 3 is a probing test of a conventional surface mount type printed circuit board using modified wiring. FIG. 3 is a side view showing a disturbance situation. 1... Lead, 2... Printed circuit board, 3... Electrical parts, 4... Test pin, 5... Wiring for modification,
6... Dedicated pad, 7... Terminal, 8... Via hole, 10... Identification mark.
Claims (1)
部品３の端子７（以下バイアホール等と称する）
が、実質的に基板２の表面と同一平面上に配置さ
れた表面実装用プリント基板であつて、前記バイ
アホール等８，６，７の中で、プロービングテス
ト時にテスタのピンが接触すべき個所にあるもの
に、基板２表面から視認可能な識別標識１０が付
されたことを特徴とするプリント基板の構造。 A large number of via holes 8, dedicated pads 6, and terminals 7 of electrical components 3 (hereinafter referred to as via holes, etc.)
is a surface mounting printed circuit board that is arranged substantially on the same plane as the surface of the board 2, and the portions of the via holes 8, 6, and 7 that are to be contacted by the pins of the tester during the probing test. A printed circuit board structure characterized in that an identification mark 10 that is visible from the surface of the board 2 is attached to the printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14229287U JPH0453022Y2 (en) | 1987-09-19 | 1987-09-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14229287U JPH0453022Y2 (en) | 1987-09-19 | 1987-09-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6448064U true JPS6448064U (en) | 1989-03-24 |
| JPH0453022Y2 JPH0453022Y2 (en) | 1992-12-14 |
Family
ID=31408116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14229287U Expired JPH0453022Y2 (en) | 1987-09-19 | 1987-09-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0453022Y2 (en) |
-
1987
- 1987-09-19 JP JP14229287U patent/JPH0453022Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0453022Y2 (en) | 1992-12-14 |
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