JPS59187144U - Test equipment for semiconductor devices - Google Patents
Test equipment for semiconductor devicesInfo
- Publication number
- JPS59187144U JPS59187144U JP8207583U JP8207583U JPS59187144U JP S59187144 U JPS59187144 U JP S59187144U JP 8207583 U JP8207583 U JP 8207583U JP 8207583 U JP8207583 U JP 8207583U JP S59187144 U JPS59187144 U JP S59187144U
- Authority
- JP
- Japan
- Prior art keywords
- board
- test equipment
- semiconductor devices
- relay board
- insert
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Measuring Leads Or Probes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の半導体試験装置を示す断面構成図、第２
図は上記試験装置の中継ボードのプリント配線を示す平
面構成図、第３図は上記試験装置の接触ピンとプリント
配線との接触状態を示す図、第４図はこの考案の一実施
例に係る半導体装置用試験装置を示す断面構成図、第５
図は上記この考案の一実施例に係る試験装置の接触ピン
と弾性接触板との接触状態を示す図である。
１１・・・半Ｓ体ベレット、１５・・・インサートボー
ド、１６ａ、１６ｂ・・・接触ピン、１９・・・測定ヘ
ッド、３０・・・中継ボード、３１ａ、：Ｎｂ・・・・
・・ピン挿入孔、３２ａ、３２ｂ・・・・・・接触ピン
先端部、３３ａ、３３ｂ・・・・・・弾性接触板。Figure 1 is a cross-sectional configuration diagram showing a conventional semiconductor test equipment;
Figure 3 is a plan configuration diagram showing the printed wiring of the relay board of the test equipment, Figure 3 is a diagram showing the state of contact between the contact pins of the testing equipment and the printed wiring, and Figure 4 is a semiconductor device according to an embodiment of the invention. Cross-sectional configuration diagram showing the device testing device, No. 5
The figure is a diagram showing a state of contact between a contact pin and an elastic contact plate of a test device according to an embodiment of the invention. DESCRIPTION OF SYMBOLS 11... Half S body bullet, 15... Insert board, 16a, 16b... Contact pin, 19... Measuring head, 30... Relay board, 31a, :Nb...
...Pin insertion hole, 32a, 32b...Contact pin tip, 33a, 33b...Elastic contact plate.
Claims (1)
接触ピンを５定ピッチで立設したインサートボードと、
このインサートボードの接触ピンそれぞれに対応する多
数の弾性接触板を備えた中継ボードと、この中継ボード
を介して上記被測定半導体ペレットからの電気信号が供
給される測定ヘッドとを具備し、上記中継ボードの弾性
接触板は、上記インサートボードの接触ピンの先端部を
挾持するよ、うにして設けたことを特徴とする半導体装
置用試験装置。An insert board with a large number of contact pins set up at five constant pitches to derive electrical signals from the semiconductor pellet to be measured;
The relay board includes a relay board having a large number of elastic contact plates corresponding to each of the contact pins of the insert board, and a measurement head to which electrical signals from the semiconductor pellet to be measured are supplied via the relay board. 1. A test device for a semiconductor device, characterized in that the elastic contact plate of the board is provided in such a way as to sandwich the tip of the contact pin of the insert board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8207583U JPS59187144U (en) | 1983-05-31 | 1983-05-31 | Test equipment for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8207583U JPS59187144U (en) | 1983-05-31 | 1983-05-31 | Test equipment for semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59187144U true JPS59187144U (en) | 1984-12-12 |
Family
ID=30212026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8207583U Pending JPS59187144U (en) | 1983-05-31 | 1983-05-31 | Test equipment for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59187144U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003501819A (en) * | 1999-05-27 | 2003-01-14 | ナノネクサス インコーポレイテッド | Massively parallel processing interface for electronic circuits |
-
1983
- 1983-05-31 JP JP8207583U patent/JPS59187144U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003501819A (en) * | 1999-05-27 | 2003-01-14 | ナノネクサス インコーポレイテッド | Massively parallel processing interface for electronic circuits |
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