JPS6448054U - - Google Patents
Info
- Publication number
- JPS6448054U JPS6448054U JP14342187U JP14342187U JPS6448054U JP S6448054 U JPS6448054 U JP S6448054U JP 14342187 U JP14342187 U JP 14342187U JP 14342187 U JP14342187 U JP 14342187U JP S6448054 U JPS6448054 U JP S6448054U
- Authority
- JP
- Japan
- Prior art keywords
- exposed portion
- gate electrode
- electrode
- layer
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims 2
- 239000013067 intermediate product Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Description
第１図は本考案のＦＥＴの一実施例の要部断面
図、第２図、第３図は第１図に示すＦＥＴの製造
工程中間品の要部断面図、第４図は従来のＦＥＴ
の要部断面図である。
１……半導体基板、２……バツフア層、３……
活性層、５……ソース電極、６……ドレイン電極
、７……ゲート電極、８……表面空乏層、８′…
…深い表面空乏層。
Fig. 1 is a sectional view of a main part of an embodiment of the FET of the present invention, Figs. 2 and 3 are sectional views of main parts of an intermediate product in the manufacturing process of the FET shown in Fig. 1, and Fig. 4 is a sectional view of a main part of an example of the FET of the present invention.
FIG. 1... Semiconductor substrate, 2... Buffer layer, 3...
Active layer, 5... Source electrode, 6... Drain electrode, 7... Gate electrode, 8... Surface depletion layer, 8'...
...deep surface depletion layer.
Claims (1)
る半導体基板の前記活性層上に、ソース電極、ゲ
ート電極、及びドレイン電極を、ソース電極とゲ
ート電極の間及びドレイン電極とゲート電極の間
にそれぞれ露出部を設けて形成し、前記露出部直
下に表面空乏層を備えてなる電界効果トランジス
タにおいて、前記表面空乏層はその深さが前記露
出部の中央部において深く形成されていることを
特徴とする電界効果トランジスタ。 On the active layer of the semiconductor substrate having a buffer layer and an active layer on the buffer layer, a source electrode, a gate electrode, and a drain electrode are provided between the source electrode and the gate electrode and between the drain electrode and the gate electrode, respectively. In a field effect transistor formed with an exposed portion and having a surface depletion layer immediately below the exposed portion, the surface depletion layer is formed to have a deep depth in a central portion of the exposed portion. field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14342187U JPS6448054U (en) | 1987-09-18 | 1987-09-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14342187U JPS6448054U (en) | 1987-09-18 | 1987-09-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6448054U true JPS6448054U (en) | 1989-03-24 |
Family
ID=31410232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14342187U Pending JPS6448054U (en) | 1987-09-18 | 1987-09-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6448054U (en) |
-
1987
- 1987-09-18 JP JP14342187U patent/JPS6448054U/ja active Pending