JPS6446985A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a width and depth of a resist and a size of a resist aperture to be controlled independently, while improving controllability of the recess width and lift-off properties, by providing a spacer layer consisting of particular three layers under photoresist. CONSTITUTION:Under a photoresist 6 for forming a gate, there is provided a dielectric spacer layer consisting of three layers: a first layer 5 having the highest etching rate of the three for determining a recess width, a second layer 5' located thereon and having the lowest etching rate of the three for preventing wet etching of the uppermost layer and the lowermost layer 5'' having an intermediate etching rate for increasing the thickness. After the uppermost layer 5'' is etched by the wet etching process, the other two layers and the photoresist 6 are etched by RIE into identical dimensions. Further, the first layer 5 is side etched by the wet etching process until a desired recess width is obtained, and a recess is formed. In this manner, the recess width can be controlled with good reproducibility independently from a depth of the recess and a size of an aperture of the resist. Further, the lift-off properties can be also improved.