JPS6446949A - Manufacture of dielectric isolation substrate - Google Patents
Manufacture of dielectric isolation substrateInfo
- Publication number
- JPS6446949A JPS6446949A JP20333587A JP20333587A JPS6446949A JP S6446949 A JPS6446949 A JP S6446949A JP 20333587 A JP20333587 A JP 20333587A JP 20333587 A JP20333587 A JP 20333587A JP S6446949 A JPS6446949 A JP S6446949A
- Authority
- JP
- Japan
- Prior art keywords
- cavity
- groove
- single crystal
- exposed
- insulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Element Separation (AREA)
Abstract
PURPOSE:To unnecessitate strict accuracy, and prevent surely the leakage of impurity between isolation islands, by depositing a retainer layer while a cavity is formed at the bottom of a groove, and abrading the single crystal side till the cavity at the bottom of the groove is exposed. CONSTITUTION:On the surface of a semiconductor single crystal wafer 1 turning to a plurality of isolation islands, grooves 1a for isolating are formed, the whole surface of which is covered with an insulating layer 3. A retainer layer 4 is deposited in the manner in which a cavity 5 is formed on the insulating layer 3 in the groove 1a. The single crystal 1 side is abraded till the cavity in the bottom of the groove is exposed, in order to isolate the semiconductor single crystal wafer 1 into a plurality of islands 10. Then, by depositing insulator 6 on the substrate surface on which the cavities are exposed, the cavities are filled with the insulator 6, and the superfluous insulator is abraded and eliminated. Thereby, as compared with the case where the insulating layer 3 is formed on the surface of a retainer layer 4, strict accuracy is unnecessitated, and impurity can be surely prevented from leaking between the isolation islands 10.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20333587A JPS6446949A (en) | 1987-08-15 | 1987-08-15 | Manufacture of dielectric isolation substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20333587A JPS6446949A (en) | 1987-08-15 | 1987-08-15 | Manufacture of dielectric isolation substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6446949A true JPS6446949A (en) | 1989-02-21 |
Family
ID=16472310
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20333587A Pending JPS6446949A (en) | 1987-08-15 | 1987-08-15 | Manufacture of dielectric isolation substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6446949A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5114875A (en) * | 1991-05-24 | 1992-05-19 | Motorola, Inc. | Planar dielectric isolated wafer |
US5386422A (en) * | 1991-03-12 | 1995-01-31 | Kabushiki Kaisha Toshiba | Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels |
US5657270A (en) * | 1990-03-31 | 1997-08-12 | Kabushiki Kaisha Toshiba | Electrically erasable programmable read-only memory with threshold value controller for data programming |
US6128229A (en) * | 1998-09-16 | 2000-10-03 | Sony Corporation | Non-volatile semiconductor memory and method of verifying after writing and reading the same |
US6160741A (en) * | 1998-12-28 | 2000-12-12 | Fujitsu Limited | Non-volatile semiconductor memory device and erasing method for said device |
US6304485B1 (en) | 1989-04-13 | 2001-10-16 | San Disk Corporation | Flash EEprom system |
KR100319615B1 (en) * | 1999-04-16 | 2002-01-09 | 김영환 | Isolation method in seconductor device |
US6687157B1 (en) * | 2003-06-11 | 2004-02-03 | Xilinx, Inc. | Circuits and methods for identifying a defective memory cell via first, second and third wordline voltages |
USRE41021E1 (en) | 1993-09-21 | 2009-12-01 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
-
1987
- 1987-08-15 JP JP20333587A patent/JPS6446949A/en active Pending
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7283397B2 (en) | 1989-04-13 | 2007-10-16 | Sandisk Corporation | Flash EEprom system capable of selective erasing and parallel programming/verifying memory cell blocks |
US7266017B2 (en) | 1989-04-13 | 2007-09-04 | Sandisk Corporation | Method for selective erasing and parallel programming/verifying of cell blocks in a flash EEprom system |
US6414876B1 (en) | 1989-04-13 | 2002-07-02 | Sandisk Corporation | Flash EEprom system |
US6304485B1 (en) | 1989-04-13 | 2001-10-16 | San Disk Corporation | Flash EEprom system |
US5657270A (en) * | 1990-03-31 | 1997-08-12 | Kabushiki Kaisha Toshiba | Electrically erasable programmable read-only memory with threshold value controller for data programming |
US5386422A (en) * | 1991-03-12 | 1995-01-31 | Kabushiki Kaisha Toshiba | Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels |
US5114875A (en) * | 1991-05-24 | 1992-05-19 | Motorola, Inc. | Planar dielectric isolated wafer |
USRE41021E1 (en) | 1993-09-21 | 2009-12-01 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
USRE41969E1 (en) | 1993-09-21 | 2010-11-30 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
USRE41950E1 (en) | 1993-09-21 | 2010-11-23 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
USRE42120E1 (en) | 1993-09-21 | 2011-02-08 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
USRE41020E1 (en) | 1993-09-21 | 2009-12-01 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
USRE41019E1 (en) | 1993-09-21 | 2009-12-01 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
USRE41244E1 (en) | 1993-09-21 | 2010-04-20 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
USRE41456E1 (en) | 1993-09-21 | 2010-07-27 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
USRE41468E1 (en) | 1993-09-21 | 2010-08-03 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
USRE41485E1 (en) | 1993-09-21 | 2010-08-10 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
US6128229A (en) * | 1998-09-16 | 2000-10-03 | Sony Corporation | Non-volatile semiconductor memory and method of verifying after writing and reading the same |
US6160741A (en) * | 1998-12-28 | 2000-12-12 | Fujitsu Limited | Non-volatile semiconductor memory device and erasing method for said device |
KR100319615B1 (en) * | 1999-04-16 | 2002-01-09 | 김영환 | Isolation method in seconductor device |
US6687157B1 (en) * | 2003-06-11 | 2004-02-03 | Xilinx, Inc. | Circuits and methods for identifying a defective memory cell via first, second and third wordline voltages |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0046501B1 (en) | Process of forming recessed dielectric regions in a silicon substrate | |
EP0316550A3 (en) | Trench isolation means and method | |
JPS647548A (en) | Manufacture of semiconductor device | |
JPS6444065A (en) | Manufacture of reverse silicon on insulator semiconductor device with pedestal structure | |
EP0316612A3 (en) | Method of manufacturing a semiconductor device with a recess filled with wiring material | |
EP0071205A2 (en) | Method for forming high density dielectric isolation | |
TW334580B (en) | Method of manufacture semiconductor device | |
JPS6446949A (en) | Manufacture of dielectric isolation substrate | |
GB2106419A (en) | Growth of structures based on group iv semiconductor materials | |
JPS5516464A (en) | Method of forming wafer for semiconductor device | |
JPS6450439A (en) | Manufacture of semiconductor device | |
JPS6412543A (en) | Manufacture of semiconductor device | |
EP0155698A3 (en) | A method for manufacturing a semiconductor integrated circuit device provided with an improved isolation structure | |
JPS6425433A (en) | Manufacture of semiconductor device | |
JPS57204148A (en) | Manufacture of semiconductor device | |
JPS6457717A (en) | Manufacture of semiconductor device | |
JPS5723217A (en) | Manufacture of semiconductor device | |
JPS5756942A (en) | Manufacture of silicon semiconductor device | |
JPS57109353A (en) | Semiconductor device | |
JPS57211747A (en) | Manufacture of semiconductor device | |
JPS6459940A (en) | Manufacture of semiconductor device | |
JPS6473738A (en) | Manufacture of semiconductor device | |
JPS5783042A (en) | Manufacture of semiconductor device | |
JPS56104446A (en) | Semiconductor device | |
JPS6457641A (en) | Manufacture of semiconductor device |