JPS6442849A - Capacitor built-in type semiconductor device - Google Patents

Capacitor built-in type semiconductor device

Info

Publication number
JPS6442849A
JPS6442849A JP20020487A JP20020487A JPS6442849A JP S6442849 A JPS6442849 A JP S6442849A JP 20020487 A JP20020487 A JP 20020487A JP 20020487 A JP20020487 A JP 20020487A JP S6442849 A JPS6442849 A JP S6442849A
Authority
JP
Japan
Prior art keywords
conductor layer
divided
conductor
parts
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20020487A
Other languages
Japanese (ja)
Other versions
JPH0581188B2 (en
Inventor
Yoichi Miyasaka
Shogo Matsubara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20020487A priority Critical patent/JPS6442849A/en
Publication of JPS6442849A publication Critical patent/JPS6442849A/en
Publication of JPH0581188B2 publication Critical patent/JPH0581188B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enhance the reliability and the yield by a method wherein one conductor layer of respective layers is divided into multiple parts electrically insulated from one another to form multiple capacitors to be used selectively. CONSTITUTION:A conductor layer 3 on a dielectric layer 2 is divided into two conductor layers 3a, 3b electrically insulated from each other while at least one of these conductor layers 3a, 3b,i.e., the conductor layer 3a is connected to a power supply electrode 51a of a semiconductor chip 6 by a bonding wire 6. When the conductor layer 3 is divided into two parts 3a, 3b, the effect of any defect in the film of dielectric layer 2 can be lessened by half compared with the case when the conductor layer 3 is not divided into two parts 3a, 3b. Furthermore, in such a constitution, two of the same capacitors are formed so that the conductor layer in the side meeting the requirements for characteristic specifications by the inspection during the intermediate processes may be used selectively. Through these procedures, the reliability and the yield can be enhanced.
JP20020487A 1987-08-10 1987-08-10 Capacitor built-in type semiconductor device Granted JPS6442849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20020487A JPS6442849A (en) 1987-08-10 1987-08-10 Capacitor built-in type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20020487A JPS6442849A (en) 1987-08-10 1987-08-10 Capacitor built-in type semiconductor device

Publications (2)

Publication Number Publication Date
JPS6442849A true JPS6442849A (en) 1989-02-15
JPH0581188B2 JPH0581188B2 (en) 1993-11-11

Family

ID=16420533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20020487A Granted JPS6442849A (en) 1987-08-10 1987-08-10 Capacitor built-in type semiconductor device

Country Status (1)

Country Link
JP (1) JPS6442849A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008251901A (en) * 2007-03-30 2008-10-16 Fuji Electric Device Technology Co Ltd Composite semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5439855A (en) * 1977-09-05 1979-03-27 Hitachi Ltd Method of making thin film capacitor
JPS61108160A (en) * 1984-11-01 1986-05-26 Nec Corp Semiconductor device with built-in capacitor and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5439855A (en) * 1977-09-05 1979-03-27 Hitachi Ltd Method of making thin film capacitor
JPS61108160A (en) * 1984-11-01 1986-05-26 Nec Corp Semiconductor device with built-in capacitor and manufacture thereof

Also Published As

Publication number Publication date
JPH0581188B2 (en) 1993-11-11

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