JPH0581188B2 - - Google Patents
Info
- Publication number
- JPH0581188B2 JPH0581188B2 JP62200204A JP20020487A JPH0581188B2 JP H0581188 B2 JPH0581188 B2 JP H0581188B2 JP 62200204 A JP62200204 A JP 62200204A JP 20020487 A JP20020487 A JP 20020487A JP H0581188 B2 JPH0581188 B2 JP H0581188B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- capacitor
- semiconductor device
- semiconductor
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 48
- 239000003990 capacitor Substances 0.000 claims description 29
- 239000004020 conductor Substances 0.000 claims description 23
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 239000000919 ceramic Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005219 brazing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はコンデンサ内蔵型半導体装置に関し、
特にリードフレーム等の半導体チツプ搭載部上に
誘電体層と導電体層とを積層しコンデンサを形成
する構造のコンデンサ内蔵型半導体装置に関す
る。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device with a built-in capacitor;
In particular, the present invention relates to a capacitor-embedded semiconductor device having a structure in which a dielectric layer and a conductive layer are stacked on a semiconductor chip mounting portion such as a lead frame to form a capacitor.
従来、半導体装置を電子装置に実装する場合、
半導体チツプ等から発生したノイズによる誤動作
を防止するために、半導体装置の電源線と接地線
との間に個別のコンデンサが挿入されていた。
Conventionally, when mounting a semiconductor device on an electronic device,
In order to prevent malfunctions due to noise generated from semiconductor chips, etc., individual capacitors have been inserted between the power supply line and the ground line of semiconductor devices.
この様な、半導体装置の外部にコンデンサを実
装する方法は、半導体装置とコンデンサとの間の
リード線のインダクタンス等によりノイズ低減効
果が十分でないこと、及びコンデンサを半導体装
置毎に実装しなくてはならないために、プリント
配線板の実装密度を低下させるなどの問題点があ
つた。そこでこれら問題点を解決するために、最
近ではコンデンサを半導体装置に内蔵するものが
いくつか試みられている。 This method of mounting a capacitor outside the semiconductor device has the disadvantage that the noise reduction effect is not sufficient due to the inductance of the lead wire between the semiconductor device and the capacitor, and the capacitor must be mounted for each semiconductor device. As a result, there were problems such as lowering the mounting density of printed wiring boards. In order to solve these problems, several attempts have recently been made to incorporate a capacitor into a semiconductor device.
従来のコンデンサ内蔵型半導体装置の例として
は、特公昭49−5392号公報、同56−129348号公報
及び同57−113261号公報などに示されるように、
セラミツクパツケージ内部またはセラミツクパツ
ケージのキヤビテイ内部にコンデンサを内蔵する
方法及びセラミツクパツケージのセラミツク基板
積層間にコンデンサをはさみこんで実施する方法
がある。 Examples of conventional semiconductor devices with built-in capacitors include Japanese Patent Publication No. 49-5392, Japanese Patent Publication No. 56-129348, and Japanese Patent Publication No. 57-113261.
There are a method in which a capacitor is built into a ceramic package or a cavity of a ceramic package, and a method in which a capacitor is sandwiched between laminated ceramic substrates of a ceramic package.
これに対し、大量かつ安値に生産されるプラス
チツクパツケージについては、前記セラミツクパ
ツケージにおけるコンデンサ内蔵方法の適用は、
製造が困難で量産性に乏しいこと、またプラスチ
ツクパツケージの構造上、極めて困難であること
の理由から実施され難く、具体的な例は少ない
が、もつとも実用的と考えられるものとして特開
昭61−108160号公報に開示されているものがあ
る。 On the other hand, for plastic packages that are produced in large quantities and at low prices, the method of incorporating capacitors in ceramic packages cannot be applied.
It is difficult to implement because it is difficult to manufacture and has low mass productivity, and the structure of the plastic package is extremely difficult, and there are few concrete examples, but it is considered to be practical. There is one disclosed in Publication No. 108160.
第２図は、特開昭61−108160号公報に開示され
ている方法を説明するため半導体装置の断面図で
ある。 FIG. 2 is a sectional view of a semiconductor device for explaining the method disclosed in Japanese Unexamined Patent Publication No. 108160/1983.
第２図に示すように、通常、金属製のリードフ
レーム１の半導体チツプ搭載部１１の上表面に誘
電率の高い物質からなる第１の誘電体層２が形成
され、第１の誘電体層２の上表面に第１の導電体
層３ｄが形成され、第１の導電体層３ｄの上表面
にこの導電体層３ｄの一部を露出させて第２の誘
電体層２ｂが形成され、第２の誘電体層２ｂの上
表面に第１の導電体層３ｄと分離して、第２の導
電体層３ｅが形成されている。さらに、第２の導
電体層３ｅの上には金属ろう材等の導電性接着剤
４ａによつて半導体チツプ５が搭載固着されてい
る。この半導体チツプ５の上面には、第１の電源
電極５１ａと第２の電源電極５１ｂとを含む複数
の電極が形成されており、第１の電源電極５１ａ
は露出している部分で第１の導電体層３ｄと、ま
た第２の電源電極５１ｂは半導体チツプ搭載部１
１とそれぞれボンデイングワイヤ６によつて電気
的に接続されている。 As shown in FIG. 2, a first dielectric layer 2 made of a material with a high dielectric constant is normally formed on the upper surface of a semiconductor chip mounting portion 11 of a lead frame 1 made of metal. A first conductor layer 3d is formed on the upper surface of the first conductor layer 3d, and a second dielectric layer 2b is formed on the upper surface of the first conductor layer 3d by exposing a part of the conductor layer 3d. A second conductor layer 3e is formed on the upper surface of the second dielectric layer 2b, separated from the first conductor layer 3d. Further, a semiconductor chip 5 is mounted and fixed on the second conductor layer 3e with a conductive adhesive 4a such as a metal brazing material. A plurality of electrodes including a first power supply electrode 51a and a second power supply electrode 51b are formed on the upper surface of this semiconductor chip 5.
is the exposed part of the first conductor layer 3d, and the second power supply electrode 51b is the exposed part of the semiconductor chip mounting part 1.
1 and are electrically connected to each other by bonding wires 6.
上記のように構成された半導体装置において
は、第１及び第２の電源電極５１ａ，５１ｂ間に
第１の誘電体層２を誘電体とし、半導体チツプ搭
載部１１と第１の導電体層３ｄとを両電極とした
コンデンサを挿入したことと等価になり、コンデ
ンサ内蔵型半導体装置を構成する。したがつて電
源配線へのノイズ混入による誤動作を防止するこ
とが出来る。 In the semiconductor device configured as described above, the first dielectric layer 2 is a dielectric between the first and second power supply electrodes 51a and 51b, and the semiconductor chip mounting portion 11 and the first conductive layer 3d are This is equivalent to inserting a capacitor with and as both electrodes, and constitutes a capacitor built-in semiconductor device. Therefore, malfunctions due to noise entering the power supply wiring can be prevented.
またこの例のように、第１及び第２の電源電極
電位と半導体チツプ５の基板底面の電位とが各々
異なる場合、電源電極・基板底面間についてもコ
ンデンサの挿入が適用できる。 Further, as in this example, when the potentials of the first and second power supply electrodes and the potential of the bottom surface of the substrate of the semiconductor chip 5 are different from each other, it is also possible to insert a capacitor between the power supply electrode and the bottom surface of the substrate.
上述した従来のコンデンサ内蔵型半導体装置に
おいて、誘電体層２，２ｂは通常スパツタ法、
CVD法あるいは酸化法によつて形成されるが、
一般にこれらのいずれの方法によつても膜中には
かなりの欠陥が存在する。通常の半導体装置にお
ける半導体チツプの面積は約20〜50mm2であり、こ
の半導体チツプの面積にほぼ等しい面積の誘電体
層においては、その面積中にかなり高い確率で欠
陥が含まれる。
In the conventional capacitor built-in semiconductor device described above, the dielectric layers 2 and 2b are usually formed by sputtering,
It is formed by CVD method or oxidation method,
Generally, there are considerable defects in the film obtained by either of these methods. The area of a semiconductor chip in a typical semiconductor device is approximately 20 to 50 mm 2 , and a dielectric layer having an area approximately equal to the area of the semiconductor chip has a fairly high probability of containing defects within that area.
上述した従来のコンデンサ内蔵型半導体装置
は、誘電体層２，２ｂ及び導電体層３ｄ，３ｅが
それぞれ半導体チツプ５の面積にほぼ等しくかつ
一体形成されているので、コンデンサの耐電圧特
性が著しく低下し、従つて製造歩留りも著しく低
下するという問題点があつた。 In the conventional capacitor built-in semiconductor device described above, the dielectric layers 2, 2b and the conductive layers 3d, 3e are each approximately equal in area to the semiconductor chip 5 and are integrally formed, so the withstand voltage characteristics of the capacitor are significantly reduced. However, there was a problem in that the manufacturing yield was also significantly reduced.
本発明の目的は、信頼性及び製造歩留りの向上
をはかることができるコンデンサ内蔵型半導体装
置を提供することにある。 An object of the present invention is to provide a capacitor built-in semiconductor device that can improve reliability and manufacturing yield.
本発明のコンデンサ内蔵型半導体装置は、少な
くとも上表面が導電体材料で形成された半導体チ
ツプ搭載部と、この半導体チツプ搭載部上に交互
に順次積層されコンデンサを形成するための少な
くとも１つの誘電体層及び導電体層と、これら誘
電体層又は導電体層上に搭載固着された半導体チ
ツプと、前記半導体チツプ搭載部上表面及び導電
体層と前記半導体チツプの対応する電極とを接続
するボンデイングワイヤとを有するコンデンサ内
蔵型半導体装置において、前記導電体層の少なく
とも１つを互いに電気的に絶縁された複数の部分
に分割し、これら分割された導電体層の少なくと
も１つを前記半導体チツプの対応する電極に接続
して構成される。
A semiconductor device with a built-in capacitor of the present invention includes a semiconductor chip mounting portion whose upper surface is made of a conductive material, and at least one dielectric material which is alternately and sequentially laminated on the semiconductor chip mounting portion to form a capacitor. a conductive layer, a semiconductor chip mounted and fixed on the dielectric layer or the conductive layer, and a bonding wire connecting the upper surface of the semiconductor chip mounting portion, the conductive layer, and the corresponding electrode of the semiconductor chip. In a semiconductor device with a built-in capacitor, at least one of the conductor layers is divided into a plurality of parts electrically insulated from each other, and at least one of the divided conductor layers is divided into a corresponding part of the semiconductor chip. connected to an electrode.
次に、本発明の実施例について図面を参照して
説明する。
Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示す断面図であ
る。 FIG. 1 is a sectional view showing one embodiment of the present invention.
この実施例が第２図に示された従来のコンデン
サ内蔵型半導体装置と相違する点は、誘電体層２
上の導電体層を、互いに電気的に絶縁された２つ
の導電体層３ａ，３ｂに分割し、これら導電体層
３ａ，３ｂの少なくとも１つ、即ち導電体層３ａ
と半導体チツプ５の電源電極５１ａとをボンデイ
ングワイヤ６で接続した点にある。 This embodiment differs from the conventional capacitor built-in semiconductor device shown in FIG.
The upper conductor layer is divided into two conductor layers 3a and 3b that are electrically insulated from each other, and at least one of these conductor layers 3a and 3b, that is, the conductor layer 3a
and the power supply electrode 51a of the semiconductor chip 5 are connected by a bonding wire 6.
この様に導電体層を２つに分割することによ
り、先ず第一に誘電体層２の膜中の欠陥の影響
は、分割しない場合にくらべてそれぞれ1/2に低
減される。更にこの構造においては同じコンデン
サーが２個形成されており、製造中間工程におけ
る検査によつて特性仕様を満足する側の導電体層
を選択して使用することができる。 By dividing the conductor layer into two in this way, first of all, the influence of defects in the dielectric layer 2 is reduced to 1/2 compared to the case where the conductor layer is not divided. Further, in this structure, two identical capacitors are formed, and it is possible to select and use the conductor layer that satisfies the characteristic specifications by inspection during the manufacturing process.
このようにして製造歩留りは、第２図に示され
た従来のものに比べて約４倍改善された。 In this way, the manufacturing yield was improved by about 4 times compared to the conventional one shown in FIG.
なお、導電体層の分割数を多くすればするほど
製造歩留りは更に改善されるが、それと共にコン
デンサの容量値は減少するため、通常の半導体装
置に必要な容量値を考えると、２ないし４分割程
度が妥当である。 The manufacturing yield will further improve as the number of divisions of the conductive layer increases, but at the same time the capacitance value of the capacitor will decrease. The degree of division is appropriate.
以上説明したように本発明は、各層の導電体層
の少なくとも１つを互いに電気的に絶縁された複
数の部分に分割し複数のコンデンサを形成し、こ
れらコンデンサの中の良品を選択して使用する構
成とすることにより、信頼性及び製造歩留りの向
上をはかることができる効果がある。
As explained above, the present invention divides at least one of the conductor layers of each layer into a plurality of parts electrically insulated from each other to form a plurality of capacitors, and selects and uses good products from among these capacitors. This configuration has the effect of improving reliability and manufacturing yield.
第１図は本発明の一実施例を示す断面図、第２
図は従来のコンデンサ内蔵型半導体装置の一例を
示す断面図である。
１……リードフレーム、２，２ａ，２ｂ……誘
電体層、３ａ〜３ｅ……導電体層、４，４ａ……
導電性接着剤、５……半導体チツプ、６……ボン
デイングワイヤ、１１……半導体チツプ搭載部、
５１ａ，５１ｂ……電源電極。
FIG. 1 is a cross-sectional view showing one embodiment of the present invention, and FIG.
The figure is a sectional view showing an example of a conventional capacitor built-in semiconductor device. 1... Lead frame, 2, 2a, 2b... Dielectric layer, 3a to 3e... Conductor layer, 4, 4a...
Conductive adhesive, 5... semiconductor chip, 6... bonding wire, 11... semiconductor chip mounting part,
51a, 51b... Power supply electrodes.
Claims (1)
半導体チツプ搭載部と、この半導体チツプ搭載部
上に交互に順次積層されコンデンサを形成するた
めの少なくとも１つの誘電体層及び導電体層と、
これら誘電体層又は導電体層上に搭載固着された
半導体チツプと、前記半導体チツプ搭載部上表面
及び導電体層と前記半導体チツプの対応する電極
とを接続するボンデイングワイヤとを有するコン
デンサ内蔵型半導体装置において、前記導電体層
の少なくとも１つを互いに電気的に絶縁された複
数の部分に分割し、これら分割された導電体層の
少なくとも１つを前記半導体チツプの対応する電
極に接続したことを特徴とするコンデンサ内蔵型
半導体装置。1. A semiconductor chip mounting part whose upper surface is made of a conductive material; at least one dielectric layer and a conductive layer which are alternately stacked on the semiconductor chip mounting part to form a capacitor;
A capacitor-embedded semiconductor having a semiconductor chip mounted and fixed on the dielectric layer or the conductive layer, and bonding wires connecting the upper surface of the semiconductor chip mounting portion, the conductive layer, and the corresponding electrodes of the semiconductor chip. In the device, at least one of the conductor layers is divided into a plurality of parts electrically insulated from each other, and at least one of the divided conductor layers is connected to a corresponding electrode of the semiconductor chip. Features a semiconductor device with a built-in capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20020487A JPS6442849A (en) | 1987-08-10 | 1987-08-10 | Capacitor built-in type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20020487A JPS6442849A (en) | 1987-08-10 | 1987-08-10 | Capacitor built-in type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6442849A JPS6442849A (en) | 1989-02-15 |
| JPH0581188B2 true JPH0581188B2 (en) | 1993-11-11 |
Family
ID=16420533
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20020487A Granted JPS6442849A (en) | 1987-08-10 | 1987-08-10 | Capacitor built-in type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6442849A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008251901A (en) * | 2007-03-30 | 2008-10-16 | Fuji Electric Device Technology Co Ltd | Composite semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5439855A (en) * | 1977-09-05 | 1979-03-27 | Hitachi Ltd | Method of making thin film capacitor |
| JPS61108160A (en) * | 1984-11-01 | 1986-05-26 | Nec Corp | Semiconductor device with built-in capacitor and manufacture thereof |
-
1987
- 1987-08-10 JP JP20020487A patent/JPS6442849A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5439855A (en) * | 1977-09-05 | 1979-03-27 | Hitachi Ltd | Method of making thin film capacitor |
| JPS61108160A (en) * | 1984-11-01 | 1986-05-26 | Nec Corp | Semiconductor device with built-in capacitor and manufacture thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008251901A (en) * | 2007-03-30 | 2008-10-16 | Fuji Electric Device Technology Co Ltd | Composite semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6442849A (en) | 1989-02-15 |
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