JPS6436212A - Pseudo random pattern generator - Google Patents

Abstract

PURPOSE:To reduce the readout cycle by storing 2<n-m> sets of patterns being the result of sequential division of a pseudo random pattern taking (2<n>-1) bits as a period by 2<m> bits each and patterns of 2<n> bits consecutive at a period of (2<n>-1) bits into a pattern memory and reading cyclicly the patterns so as to reduce the capacity of pattern memory. CONSTITUTION:A basic random pattern repeated periodically for (2<n>-1) each is sectioned into 2<n-m> sets for each 2<m> bits to be partial patterns of 2<m+1> bits in length respectively and stored in the pattern memory 23. Then the readout pattern from the memory 23 is inputted in parallel with a shift register 24 by the output of a 2<n-m>-adic counter 41, shifted by one bit by one bit shift means and the pattern generation control is adjusted by the means of write. Thus, the partial pattern read from the pattern memory 23 is shifted cyclicly and stored again in the address read from the pattern memory 23. Thus, the partial pattern read next is contained at all times with good sectioning in the pattern memory.