JPS6436213A - Pseudo random pattern generator - Google Patents

Abstract

PURPOSE:To attain small capacity of a pattern memory by forming 2<n-m>, sets of patterns being the result of sequential division of a pseudo random pattern for each 2<m> bit taking (2<n>-1) bits as a period and (2<m>-1) bits of patterns consecutive to the former patterns and storing them in a pattern memory as one word and reading and outputting them by the cyclic readout control. CONSTITUTION:A multiplexer 24 outputs one of 2<m> sets of patterns in 2<m>-bit adjacent sequentially in combination from the (2<m+1>-1) bits of patterns read from the pattern memory 23 in response to the control input. A parallel/serial conversion circuit 28 converts the output of a latch receiving the output of the multiplexer 24 for each clock into a serial pattern. Then the readout of the pattern memory is controlled and the adjustment control advancing the 2<n-m> counter by one step for each output of the 2<m>-adic counter. Thus, the partial patterns read out of the pattern memory are read cyclicly while the read part is moved sequentially. Thus, the capacity of the pattern memory is very small.