JPS55136907A - Sample holding circuit - Google Patents

Sample holding circuit

Info

Publication number
JPS55136907A
JPS55136907A JP4435179A JP4435179A JPS55136907A JP S55136907 A JPS55136907 A JP S55136907A JP 4435179 A JP4435179 A JP 4435179A JP 4435179 A JP4435179 A JP 4435179A JP S55136907 A JPS55136907 A JP S55136907A
Authority
JP
Japan
Prior art keywords
circuit
data
time
distributor
latched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4435179A
Other languages
Japanese (ja)
Inventor
Tadashi Nishino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4435179A priority Critical patent/JPS55136907A/en
Publication of JPS55136907A publication Critical patent/JPS55136907A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To produce analog outputs having equal data totally without a buffer circuit by providing contacts to be distributed but not connected to the circuit of a distributor.
CONSTITUTION: Digital signals of a plurality of systems are divided, when having a number of bit configuration, in predetermined sequence in time division manner into lower and upper bits, which are sequentially latched in latch circuits 10, 20, respectively. When the output is produced as a signal having ten bits for example, eight bit data D0WD7 are latched in the latch circuit 10 by the initial instruction, and two bit data D0 and D1 are latched in the latch circuit 20 by the next instruction. When the data are inputted to the D/A converter 30, a distributor 40 is operated synchronously with the clock signal for latching the latch circuits 10, 20. The contacts a-p of the distributor 40 are shortcircuited during the time longer than the time when the latch circuits 10, 20 are operating at least and the contacts a-b and a-c are shortcircuited during the time except the previous time to hold the data in the holding circuit 50 so as to obtain analog outputs q1, q2.
COPYRIGHT: (C)1980,JPO&Japio
JP4435179A 1979-04-13 1979-04-13 Sample holding circuit Pending JPS55136907A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4435179A JPS55136907A (en) 1979-04-13 1979-04-13 Sample holding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4435179A JPS55136907A (en) 1979-04-13 1979-04-13 Sample holding circuit

Publications (1)

Publication Number Publication Date
JPS55136907A true JPS55136907A (en) 1980-10-25

Family

ID=12689085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4435179A Pending JPS55136907A (en) 1979-04-13 1979-04-13 Sample holding circuit

Country Status (1)

Country Link
JP (1) JPS55136907A (en)

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