JPS567546A - Bit synchronizing circuit - Google Patents

Abstract

PURPOSE:To prevent the missing of data, by locating the operating speed of each signal near the limit of ability of circuit elements, through the closed approach of the repetitive period of the input data, input clock signal and output clock signal to take bit synchronism. CONSTITUTION:The digital signal is controlled with the output of the four frequency division counter 34 and sequentially stored one by one bit at the elastic memory 36 having the capacity of 4-bit, and latched for the period of 4/f1 (where; f1 is the repetitive frequency). The selection pulse generating circuit 38 selects four data of the memory 36, based on the output of the changing point detection circuit 37 which detects the changing point of the output signal of the counter 34 by taking the inverting clock as shift pulse. The output of the memory 36 is controlled at the selection pulse signal at the circuit 38 at the selector 39, four data are sequentially selected one by one and are replaced into data train of one row. The output of the selector 39 is in re-timing by taking the output of the missing clock generating circuit 310 as trigger at the re-timing circuit 311.