SU926725A1 - Storage unit testing device - Google Patents

Description

(5) DEVICE FOR MONITORING MEMORY BLOCKS

I

The invention relates to storage devices (RAM), in particular to memory control devices.

A device is known for controlling a memory device containing blocks for the formation of control codes D 1.

The closest to the present invention is a device for monitoring storage modules containing a shift register, an initial state register, modulo-two adders, an in ({jurmatization register, control circuit, address register, mask registers, and I.

The known device implements linear and nonlinear codes, which allows a significant increase in the number of C2 verification tests.

The disadvantages of the known devices are falsity and low speed at (| yrmirovaniya tests, which makes it impossible to control the memory at the limiting frequencies of circulation.

The purpose of the invention is to increase the speed of the device for monitoring memory blocks.

The goal is achieved by the fact that in a device for controlling memory blocks containing a driver of standards, the inputs of which are connected to the output group of the control node, a shift register whose control input is connected to the first output

10 of the control unit, the comparison circuit, the outputs of which are connected to the inputs of the control unit, and one inputs of the comparison circuit are the inputs of the device, additional elements are introduced

Claims (2)

15 EXCLUSIVE OR, one inputs of which are connected to the outputs of the pattern maker, other inputs to one output of the shift register, and outputs of the EXCESSER. OR elements 20 are connected to other inputs of the comparison circuit and are outputs of the device, and a trigger, one input of which is connected to another the output of the shift register 39, the other input is connected to the second output of the control unit, and the output of the trigger is connected to the information input of the shift register. The block diagram of the device for KOHtpol memory blocks is shown in the drawing, -The device contains shaper 1. Standards, shift register 2, elements EXCLUSIVE OR 3, control circuit k, control unit 5, trigger 6, monitored memory block 7, control The block inputs 8, the outputs 9 of the comparison circuit and the control inputs 10 of the shift register. The device works as follows. Initially, the signal from control block 5 sends a zero reference code from the generator of 1 standards and a zero shift register code 2 to the EXCLUSIVE OR 3 elements. The code of the EXCLUSIVE or C elements is written to all addresses of the monitored memory block (address codes and control signals for the memory block forms the control node). Then, a cycle of reading and comparing information to all addresses is performed by the comparison circuit k. The comparison result from the outputs 9 enters the control unit 5. In the absence of incomparability, the node 5 of the control signal received at the input 1U, shifts the shift register code 2. At the same time, a unit is written to its zero bit. Then the code is repeated from the EXCLUSIVE OR 3 elements at all addresses of the memory block, and then read and compare in circuit 4 of the comparison. The presence in one of the bits of the code read from the memory of a single information, different from the zero information of all other bits, allows you to read and check their mutual influence. A new shift of the shift register code is then made, with the units being written in zero and first bits, which allows for the writing, reading, and comparison to determine the mutual effects of these bits and all the others. The write, read and compare cycles at zero reference are repeated until the shift register 2 is completely filled with ones. Its last bit is connected to the input of trigger 6, The signal at input 1 from the control node records the single information of the last bit of the shift register 2 to trigger 6. After that, the memory block is monitored while all bits are filled with zero. units, and the shaper of 1 patterns generates in the first cycle of writing and reading at all addresses a sequence of codes corresponding to the change in the 0th bit of the address, in the second cycle a sequence of codes corresponding to the change in the 1st bit yes addresses, etc., in the cycle of the n-th address bit (where n, N is the capacity of the monitored memory block. To prepare the code to be written to the memory block, just one clock cycle of the shift register 2 or one clock of the former 1 reference is sufficient. The speed of the device is increased, since no transfer of the reference code between registers, modulo two summaries, etc., is used. Formula for monitoring memory blocks containing the pattern former, the inputs of which are connected to the output group of the control node, are shifted A new register, the control input of which is connected to the first output of the control node, the comparison circuit, the outputs of which are connected to the inputs of the control node, and one input of the comparison circuit are device inputs, characterized in that, in order to increase the speed of the device, it contains EXCLUSIVE elements OR, some inputs of which are connected to the outputs of the standards generator, other inputs to one outputs of the shift register, and outputs of the EXPLUSIVE elements OR are connected to other inputs of the comparison circuit and are outputs Twa and trigger kotoro.go one input connected to another output of the shift register, the other input - to control the second output node, and a trigger output connected to a data input of the shift register. Sources of information taken into account in the examination 1, USSR Author's Certificate No. 526952, cl. G 11 C 29/00, 1975. 2, USSR Copyright Certificate No., cell, GII C 29/00, 1972 (prototype).