SU1667159A2 - Memory checking device - Google Patents

Abstract

This invention relates to memory devices. The purpose of the invention is to increase the speed of the device. The invention allows for the verification of storage devices by forming abbreviated monitoring tests. The goal is achieved by introducing into the device the third and fourth registers and the group of elements OR. The use of the invention leads to a decrease in the time of checking the memory blocks of large information capacity. 1 il.

Description

The invention relates to storage devices and is an improvement of the invention according to the author. St. No. 739658.

The purpose of the invention is to increase the speed of the device.

The drawing shows a block diagram of a memory control device.

The device contains registers 1-4, a group of elements OR 5, a switch 6, a control unit 7, a test generation unit 8, a trigger 9, a write-read pulse generation unit 10, a receiving register 11, a comparison unit 12, a stop unit 13, a local control unit 14.

The address width P of the checked memory consists of bits of the register of rows m and columns n in the memory matrix.

R t x p.

In order to organize address iteration over a cross or a row (column) in a testing test, it is necessary to provide the ability to autonomously change the corresponding

Part m or n bits of the register of the address of the memory being scanned.

The size of all four registers 1-4, as well as the number of elements OR 5 and the width of the switch 6 are equal and correspond to the maximum possible number of address bits for the checked memory.

The bits of registers 1 and 3 under the influence of the outputs of register 4 can have two modes of operation, counting, if their inputs are supplied with a single potential from the output of the corresponding register bit 4 or the forced retention mode in a single state that does not affect the ability to work counting mode of the subsequent bits of this register. Both modes of operation of registers 1 and 3 are set by the output potentials of register 4, the first one and the second zero. In this case, it is possible to count, starting with the register bit, which has the first permission. Thus setting the positional

with

with

about o VI

ate yu

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code in register A, you can determine the number of the first counting bits of registers 1 and 3.

The device works as follows.

When forming cross-type address transitions from the control unit 7, the setup signals are sent to the test-forming unit 8 and the register 4. Register 4 provides unit and zero levels for bits 1 and 3, for example, as shown in the drawings: from the direct outputs 0–4 bits are single and from 5-9 zero (and vice versa, for inverse outputs). At the output of the bits of registers 1 and 3, forcibly set by register 4 to a single-state hold mode, there is a level that permits passing through the corresponding element OR 5 of the group of signals of the same bit to another O register, operating in counting mode.

The memory check starts from the initial zero address transmitted by the switch to register 2. The output of the elements of OR 5 group is the address of the zero column and the first row. According to the signals from the control units 7 and the formation of tests 8, trigger 9 and the write-read pulse shaping unit 10 are started, and at two addresses determined by register 2, the output state of the elements of the OR 5 group and tripler H, the corresponding teggy Next, a unit is added to the pe (source 1, increasing the address of the string, and a similar treatment is performed on a new pair of addresses.

Similarly, the address is processed at the remaining addresses of the zero column before the register 1 reaches the address one less than the initial one, i.e. zero. Control block 7 stops adding units to register 1, and the signaling of these signals, register 3, which determines the address status of the first column, begins. After accessing this new pair of addresses, a call is made to a different address pair, which is part of register 3 (second column address), and so on. until the register 3 reaches the initial state equal to the register 1 state. The first step of forming the address transitions ends with an increase of register 2 state units (a shift occurs, the center of the cross). The second and subsequent cycles are performed meaningfully with the addition of one unit of Reshvres 1 and 3 until they reach the initial state equal to the state n of part n of register 2 for register 3 and part m of register 2 for register 1. The type of address for each of the addresses in The pair to be tested is determined by the write-read pulse-shaping unit 10, and those facing an address in the pair — by trigger 9, depending on the type of test.

If it is necessary to change the size of the registers from the control unit 7, the register 4 receives signals to change the state of its bits.

To form address transitions within a row or column in the reference cycle, addresses are searched only by one of registers 1 or 3, while the second is constantly in a state equal to the state of the corresponding part m or n of register 2.

When forming address transitions for strings of type N2, where the bits of register 4 from control unit 7 are set to the same state and one of registers 1 or 3 is working on the full volume of addresses, forming an address paired with the address of register 2. Adding a unit is performed only in That register 1 or 3, which operates in the account mode.

The information read from the checked memory block is received on the register 11, compared with the reference one in the comparison block 12, which, if there is a mismatch, starts the stop block 13. The signal from the stop block 13 stops the operation of the local control block 14.

The device allows the formation of shorter N3 / 2 tests, which leads to a decrease in the time for checking large-capacity storage units.

Claims (1)

Invention Formula A device for controlling memory by aut. St. No. 739658, characterized in that, in order to improve the speed of the device, the third and fourth address registers and the group of OR elements are entered into it, the outputs of the first address register through the first inputs of the OR elements of the group are connected to the first input of the switch, the second inputs of the OR elements of the group are connected with outputs of bits of the third address register, whose inputs are bitwise connected with inverse inputs of the fourth address register, whose forward outputs are bitwise connected with inputs of the first address register, input of the fourth the address register is connected to one of the outputs of the control unit.