JPS6428949A - Semiconductor input protective device - Google Patents
Semiconductor input protective deviceInfo
- Publication number
- JPS6428949A JPS6428949A JP62185919A JP18591987A JPS6428949A JP S6428949 A JPS6428949 A JP S6428949A JP 62185919 A JP62185919 A JP 62185919A JP 18591987 A JP18591987 A JP 18591987A JP S6428949 A JPS6428949 A JP S6428949A
- Authority
- JP
- Japan
- Prior art keywords
- impurity layer
- layer
- type
- oxide film
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 230000001681 protective effect Effects 0.000 title 1
- 239000012535 impurity Substances 0.000 abstract 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
PURPOSE:To prevent the occurrence of a leakage current in a region where a drain impurity diffusion layer comes into contact with a gate oxide film by a method wherein a first impurity layer and a second impurity layer of an opposite conductivity type which are separated by an insulating film and which are extended in parallel are formed in a semiconductor substrate of one conductivity type and a third impurity layer of the opposite conductivity type is formed to be deeper than the first impurity layer and the second impurity layer. CONSTITUTION:A first N-type impurity layer 104 connected to a ground terminal or a power- supply terminal via an aluminum wiring part 111 and a polycrystalline silicon layer 106 and a second N-type impurity layer 103 connected to an input terminal via a bonding pad 101 and the polycrystalline silicon layer 106 are formed on a P-type silicon substrate 113 in such a way that they are separated by a thick silicon oxide film 112B and are parallel with each other. Third N-type impurity layers 114A, 114B are formed in such a way that they come into contact with the first N-type impurity layer 104 and the thick silicon oxide film 112B as well as the second N-type impurity layer 103 and the thick silicon oxide film 112B, respectively, and that they are deeper than the first impurity layer and the second impurity layer 104, 103. By this setup, a width of a depletion layer in a boundary region between the second N-type impurity region 103 on the side of the input terminal and the thick silicon oxide film can be narrowed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62185919A JPS6428949A (en) | 1987-07-24 | 1987-07-24 | Semiconductor input protective device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62185919A JPS6428949A (en) | 1987-07-24 | 1987-07-24 | Semiconductor input protective device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6428949A true JPS6428949A (en) | 1989-01-31 |
Family
ID=16179172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62185919A Pending JPS6428949A (en) | 1987-07-24 | 1987-07-24 | Semiconductor input protective device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6428949A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0341770A (en) * | 1989-07-10 | 1991-02-22 | Nec Corp | Semiconductor device |
-
1987
- 1987-07-24 JP JP62185919A patent/JPS6428949A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0341770A (en) * | 1989-07-10 | 1991-02-22 | Nec Corp | Semiconductor device |
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