JPS6428831A - Hybrid ic - Google Patents

Hybrid ic

Info

Publication number
JPS6428831A
JPS6428831A JP18529687A JP18529687A JPS6428831A JP S6428831 A JPS6428831 A JP S6428831A JP 18529687 A JP18529687 A JP 18529687A JP 18529687 A JP18529687 A JP 18529687A JP S6428831 A JPS6428831 A JP S6428831A
Authority
JP
Japan
Prior art keywords
chip
wires
housed
recessed part
parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18529687A
Other languages
Japanese (ja)
Inventor
Toshio Usuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP18529687A priority Critical patent/JPS6428831A/en
Publication of JPS6428831A publication Critical patent/JPS6428831A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

PURPOSE:To prevent a semiconductor element from deterioration due to the generation of heat as well as to prevent the occurrence of defectives due to disconnection by a method wherein a copper plate placed with a semiconductor chip is housed in a recessed part provided on an alumina substrate. CONSTITUTION:A copper plate 4 placed with a semiconductor chip 3 is housed in a recessed part 7 provided on an alumina substrate 1. As the plate placed with the chip is housed in the recessed part in such a way, the head between the surface of the chip 3 and metallized parts 2 is reduced, a stress to be applied to the bonding neck parts of emitter wires 6a and base wires 6b can be reduced and the occurrence of defectives due to the disconnection of the wires can be prevented. Moreover, the length of the wires 6a to be provided from the chip 3 to the parts 2 can be shortened and an increase in the efficiency of a device and an increase in the output of the device can be contrived.
JP18529687A 1987-07-23 1987-07-23 Hybrid ic Pending JPS6428831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18529687A JPS6428831A (en) 1987-07-23 1987-07-23 Hybrid ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18529687A JPS6428831A (en) 1987-07-23 1987-07-23 Hybrid ic

Publications (1)

Publication Number Publication Date
JPS6428831A true JPS6428831A (en) 1989-01-31

Family

ID=16168378

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18529687A Pending JPS6428831A (en) 1987-07-23 1987-07-23 Hybrid ic

Country Status (1)

Country Link
JP (1) JPS6428831A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461201A (en) * 1993-01-22 1995-10-24 Siemens Aktiengesellschaft Insulating part with integral cooling element
US5463530A (en) * 1993-02-05 1995-10-31 The Bergquist Company Dual sided laminated semiconductor mounting

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461201A (en) * 1993-01-22 1995-10-24 Siemens Aktiengesellschaft Insulating part with integral cooling element
US5463530A (en) * 1993-02-05 1995-10-31 The Bergquist Company Dual sided laminated semiconductor mounting

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