JPS6425400A - Circuit for testing access time - Google Patents

Circuit for testing access time

Info

Publication number
JPS6425400A
JPS6425400A JP62181148A JP18114887A JPS6425400A JP S6425400 A JPS6425400 A JP S6425400A JP 62181148 A JP62181148 A JP 62181148A JP 18114887 A JP18114887 A JP 18114887A JP S6425400 A JPS6425400 A JP S6425400A
Authority
JP
Japan
Prior art keywords
address
memory
tested
selector
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62181148A
Other languages
Japanese (ja)
Inventor
Yutaka Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62181148A priority Critical patent/JPS6425400A/en
Publication of JPS6425400A publication Critical patent/JPS6425400A/en
Pending legal-status Critical Current

Links

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To execute the measurement of more exact access time by feeding back address information to be read out from a memory to be tested as an address signal through a feedback address circuit and a selector and forming the reading actuation of the memory to be tested. CONSTITUTION:When a value of zero is set in external address signal inputs A0-A7 while a read-write selecting terminal 4 is made into '0' and the memory 1 to be tested is held in a reading state, the memory 1 to be tested selects a zero address and an address signal with the value 1 corresponding to the address information stored in the above is outputted on a feedback address circuit 5. Under this state, when an selector switching terminal 3 is made into '1' and a selector 2 is switched to the input side of the feedback address signal, the memory 1 to be tested selects the one address this time, since it newly accepts, as its own address, the address signal with the value of one fed back through the feedback address circuit 5 and the selector 2. Thus, the continuous reading out actuation of the tested memory 1 is formed. By this reason, the measurement of the more exact access time can be executed.
JP62181148A 1987-07-22 1987-07-22 Circuit for testing access time Pending JPS6425400A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62181148A JPS6425400A (en) 1987-07-22 1987-07-22 Circuit for testing access time

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62181148A JPS6425400A (en) 1987-07-22 1987-07-22 Circuit for testing access time

Publications (1)

Publication Number Publication Date
JPS6425400A true JPS6425400A (en) 1989-01-27

Family

ID=16095723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62181148A Pending JPS6425400A (en) 1987-07-22 1987-07-22 Circuit for testing access time

Country Status (1)

Country Link
JP (1) JPS6425400A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6115783A (en) * 1996-08-15 2000-09-05 Nec Corporation Integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6115783A (en) * 1996-08-15 2000-09-05 Nec Corporation Integrated circuit
US6321291B1 (en) 1996-08-15 2001-11-20 Nec Corporation Method of measuring the speed of a memory unit in an integrated circuit

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