JPS642257B2 - - Google Patents

Info

Publication number
JPS642257B2
JPS642257B2 JP6510680A JP6510680A JPS642257B2 JP S642257 B2 JPS642257 B2 JP S642257B2 JP 6510680 A JP6510680 A JP 6510680A JP 6510680 A JP6510680 A JP 6510680A JP S642257 B2 JPS642257 B2 JP S642257B2
Authority
JP
Japan
Prior art keywords
terminals
frequency
input
output
time slot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6510680A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56161735A (en
Inventor
Yoshitaka Muto
Shinji Seto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6510680A priority Critical patent/JPS56161735A/ja
Publication of JPS56161735A publication Critical patent/JPS56161735A/ja
Publication of JPS642257B2 publication Critical patent/JPS642257B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J4/00Combined time-division and frequency-division multiplex systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
JP6510680A 1980-05-16 1980-05-16 Signal transmission circuit Granted JPS56161735A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6510680A JPS56161735A (en) 1980-05-16 1980-05-16 Signal transmission circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6510680A JPS56161735A (en) 1980-05-16 1980-05-16 Signal transmission circuit

Publications (2)

Publication Number Publication Date
JPS56161735A JPS56161735A (en) 1981-12-12
JPS642257B2 true JPS642257B2 (OSRAM) 1989-01-17

Family

ID=13277305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6510680A Granted JPS56161735A (en) 1980-05-16 1980-05-16 Signal transmission circuit

Country Status (1)

Country Link
JP (1) JPS56161735A (OSRAM)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6436134A (en) * 1987-07-31 1989-02-07 Nec Corp Transmission power amplifying circuit
US4995055A (en) * 1988-06-16 1991-02-19 Hughes Aircraft Company Time shared very small aperture satellite terminals

Also Published As

Publication number Publication date
JPS56161735A (en) 1981-12-12

Similar Documents

Publication Publication Date Title
CA2048561A1 (en) High frequency power amplifier with high efficiency and low distortion
US4531098A (en) Wide dynamic range amplifier with second harmonic signal cancellation
US4453130A (en) Switched-capacitor stage with differential output
JP2665251B2 (ja) マイクロ波増幅器
JPS642257B2 (OSRAM)
JP3758849B2 (ja) データ変換装置
EP0443368B1 (en) Constant-amplitude wave combination type amplifier
JPH0936663A (ja) 周波数変換回路
JP2697650B2 (ja) フィードフォワード増幅器
JP3508835B2 (ja) 複数周波数帯域増幅回路
CN114244391B (zh) 一种射频组件
KR0138078B1 (ko) 선형증폭기의 상호 변조 왜곡신호 제거회로
JP2000261345A (ja) 狭帯域干渉波制限装置およびそれを用いた通信装置
EP0103410B1 (en) Switched-capacitor stage with differential output
JP2984548B2 (ja) デジタル振幅変調送信機
JPH0728475B2 (ja) マルチウェイスピ−カ装置用ネットワ−ク
JPH09186618A (ja) ラジオ受信機
JP3439637B2 (ja) 高周波装置
JP2925333B2 (ja) プッシュボタン信号発生回路
JPH06216671A (ja) 高周波増幅装置
JP2001203555A (ja) 弾性表面波フィルタの配置構造
SU1288640A1 (ru) Устройство дл обработки сигналов
JP3050302B2 (ja) 衛星通信地球局
JP3371838B2 (ja) フィードフォワード増幅器
KR100746106B1 (ko) 신호처리용 디지털 보드의 마스터클럭 제거 장치