JPS6419731A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6419731A
JPS6419731A JP17471887A JP17471887A JPS6419731A JP S6419731 A JPS6419731 A JP S6419731A JP 17471887 A JP17471887 A JP 17471887A JP 17471887 A JP17471887 A JP 17471887A JP S6419731 A JPS6419731 A JP S6419731A
Authority
JP
Japan
Prior art keywords
layer
resist
type
epitaxially grown
inp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17471887A
Other languages
Japanese (ja)
Inventor
Emiko Yoshinari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17471887A priority Critical patent/JPS6419731A/en
Publication of JPS6419731A publication Critical patent/JPS6419731A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent an epitaxial layer from being contamated with a resist by a method wherein at least one layer, which constitutes no element, is formed on the surface of the epitaxial layer constituting an element, a resist having a necessary pattern is formed thereon, an element forming process is conducted, and then the resist and the epitaxial layer, which constitutes no element, are removed by etching. CONSTITUTION:An InGaAsP active layer 2 is epitaxially grown on a P-type InP substrate 1, and then a P-type InP clad layer 3 and a P-type InGaAd cap layer 4 are epitaxially grown. Besides, InP layer 5, which does not constitute in LED, is epitaxially grown thereon. Then, a resist 6 is coated on the above- mentioned layer 5, exposing and developing operations are conducted, and the resist 6 is patterned. A groove 7 is formed by etching using said resist 6 as a mask. Subsequently, the resist 6 is removed by conducting organic cleaning, the InP layer 5 is removed with hot nitric acid, and the clean surface of the P-type InGaAsP cap layer 4 is obtained.
JP17471887A 1987-07-15 1987-07-15 Manufacture of semiconductor device Pending JPS6419731A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17471887A JPS6419731A (en) 1987-07-15 1987-07-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17471887A JPS6419731A (en) 1987-07-15 1987-07-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6419731A true JPS6419731A (en) 1989-01-23

Family

ID=15983434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17471887A Pending JPS6419731A (en) 1987-07-15 1987-07-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6419731A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08316219A (en) * 1995-05-19 1996-11-29 Nec Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08316219A (en) * 1995-05-19 1996-11-29 Nec Corp Manufacture of semiconductor device

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