JPS641878B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for effectively controlling data transfer between a magnetic bubble storage device and an external storage device such as a RAM.

[Prior art and its problems]

When transferring data between a magnetic bubble storage device and an external storage element such as RAM, the host CPU
In order to make effective use of data and improve transfer efficiency,
Reduces CPU involvement and dedicates data transfer control
DMA (Direct) using a DMA controller
Memory Access) method is known.

FIG. 1 is a block diagram showing a transfer control method using this DMA method. In this figure, 1 is a magnetic bubble storage device, 2 is an external storage element such as RAM, and 3 is a magnetic bubble storage device.
is a host CPU, 4 is a DMA controller, and 5 is an address decoder. When transferring data from the magnetic bubble storage device 1 side to RAM 2, the host
Generates a read command from the CPU 3 and inputs it to the magnetic bubble storage device 1 and DMA controller 4,
As a result, a transfer request signal TXRQ is input from the magnetic bubble storage device 1 to the DMA controller 4.
Then, the address decoder 5 decodes the address specified by the host CPU 3, sets it in the RAM 2, and notifies the magnetic bubble storage device 1 via the DMA controller 4, so that the DMA controller 4 disconnects the bus 6 from the host CPU 3. , connected to RAM2 via bus 7, and transferred directly to RAM2. When the transfer is completed, the DMA controller 4 sends a transfer end signal TXAK back to the magnetic bubble storage device 1.

When writing data to the magnetic bubble storage device 1, a read command is generated from the host CPU 3,
input to the magnetic bubble storage device 1 and the DMA controller 4, and as a result from the magnetic bubble storage device 1
A transfer request signal TXRQ is input to the DMA controller 4. The data at the designated address in RAM 2 is then transferred to magnetic bubble storage device 1, and when the transfer is completed, a transfer end signal TXAK is sent back to magnetic bubble storage device 1.

In addition, when the host CPU 3 reads and uses the data in the RAM 2, by disconnecting the bus 6 from the magnetic bubble storage device 1, the RAM 2 and the host
Data is transferred to and from the CPU 3.

In order to improve host CPU usage efficiency and transfer efficiency in this way, a DMA controller is required. However, when data is transferred using a DMA controller, the configuration of the DMA controller itself is complex, and the amount and cost of additional circuits tends to increase. This situation does not change even if the RAM address is fixed.

[Purpose of the invention]

The purpose of the present invention is to solve these problems in the conventional data transfer method of magnetic bubble storage devices, and to eliminate the need for complex and expensive control circuits such as DMA controllers, and to utilize the host CPU's power in the same way as the DMA method. The object of the present invention is to enable direct and efficient data transfer between a magnetic bubble storage device and an external storage element with minimal involvement.

[Structure of the invention]

The technical means according to the present invention taken to achieve the present invention includes a magnetic bubble memory element, a writing means and a reading means for the magnetic bubble memory element, and data exchange between the writing means and reading means and an external device. The device is equipped with a data transfer control means for controlling the data transfer, and the data transfer control means includes a pulse signal generation means for outputting first and second pulse signals when a data transfer request signal is input, and the data transfer control means controls the data transfer. When the request signal is output, the first pulse signal is input to the data transfer control means as a data transfer response signal, and when the data transfer direction display means indicates the first state, the second pulse signal is inputted to the data transfer control means as a data transfer response signal. A pulse signal is input to the data transfer control means as a data write signal, and when the data transfer direction display means indicates a second state, the second pulse signal is input to the data transfer control means as a data read signal. We are adopting a method to do so.

[Embodiments of the invention]

Next, how the data transfer method of the magnetic bubble storage device according to the present invention is actually implemented will be explained using an example. FIG. 2 is a block diagram showing an embodiment of a data transfer system for a magnetic bubble storage device according to the present invention. In this figure, as in the case of FIG. 1, 1 is a magnetic bubble storage device, 2 is an external storage element such as a RAM, 3 is a host CPU, and 5 is an address decoder. In the present invention, as shown in FIG.
In place of the DMA controller 4, an R/W (read/write) pulse controller 9 is provided as data transfer control means. Also, traditionally, the host
Although it was possible to arbitrarily set the address of RAM 2 as the transfer destination from the CPU 3 via the DMA controller 4, in the present invention, the address of RAM 2 is fixed.
Addresses of RAM2 are determined mechanically in a fixed order, and writing is performed. Therefore, the conventional
The bus 8 to the DMA controller 4 is no longer needed, and the bus 6 is only connected to the bus 7 to the RAM 2.

Furthermore, conventionally, the read signal line 10 and write signal line 11 that connect the host CPU 3 to the magnetic bubble storage device 1, RAM 2, and DMA controller 4 are eliminated, and the host CPU 3 is connected to the read signal line 10a and the write signal line 11b. /W pulse controller 9 only is stored. And R/
W pulse controller 9 and magnetic bubble storage device 1
Read signal line 12 and write signal line 1 between
3 is also connected to RAM2. Also, a signal line 1 for transmitting a transfer direction signal DIR indicating the direction of read and write from the magnetic bubble storage device 1.
4, the magnetic bubble storage device 1 and the R/W pulse controller 9 are connected.

In this configuration, when a read or write command is generated from the host CPU 3, a transfer request signal TXRQ is input from the magnetic bubble storage device 1 and a transfer direction signal is generated from the magnetic bubble storage device 1.
Based on DIR, R/W pulse controller 9
, a read or write pulse is created,
Input to RAM2. Therefore, by simply inputting the transfer direction signal DIR from the magnetic bubble storage device 1 to the R/W pulse controller 9, it is possible to instruct the RAM 2 in the transfer direction and perform data transfer.
There is no need to set addresses as in the past.

That is, conventionally, from the magnetic bubble storage device 1 to the RAM
In order to identify whether data is to be transferred to the magnetic bubble storage device 1 from the RAM 2 or vice versa, the DMA controller 4 sets the transfer direction based on a command from the host CPU 3. However, in the present invention, the host CPU3
When a read/write command is generated from the RAM 2, the R/W pulse controller 9 generates a read/write pulse based on the transfer direction signal DIR generated by the magnetic bubble storage device 1.
Enter. As a result, the RAM 2 can immediately recognize whether the command is a read command or a write command.

In Figure 1, DMA controller 4
Although the address of RAM2 is arbitrarily set, in the present invention, data can be written by counting pulses with a counter in the R/W pulse controller 9 and advancing the address of RAM2 in a fixed order. can. Also, from RAM2 to the host CPU
3, disconnect the bus 6 from the magnetic bubble storage device 1 and connect it to the host.
Connected to CPU3.

FIG. 3 is a block diagram showing a specific example of the R/W pulse controller 9 that performs such control.
15 is a one-shot multivibrator in the R/W pulse controller 9, and a magnetic bubble storage device 1
It receives the transfer request signal TXRQ from the magnetic bubble storage device 1, and when the transfer is completed, it returns the transfer end signal TXAK to the magnetic bubble storage device 1. Furthermore, when the transfer request signal TXRQ is input, it is transmitted through the AND gates 19, 20 and 21, 2 via the OR gates 17, 18 on the signal line 16.
Input the data request pulse to 2. host CPU
The transfer direction signal DIR indicating the transfer direction based on the command from 3 is input directly to the AND gates 19 and 22 via the OR gate 17, while via the inverter 23 and the OR gate 18.
Input to AND gates 20 and 21.

Assuming that a write command to RAM2 is now generated, the transfer direction signal DIR indicating transfer from the magnetic bubble storage device 1 to RAM2 becomes H level, and the L level pulse inverted by the inverter 23 is sent via the OR gate 18. Input to AND gates 20 and 21. Also, a write pulse is sent from the host CPU 3 to the OR gate 2 via the signal line 11a.
4 to the AND gate 21. As a result, the AND logic of the AND gate 21 is established,
A write pulse is input to RAM2. On the other hand, the transfer end signal TXAK is inverted by the inverter 26 and becomes L level, and is input to the AND gate 20 via the OR gate 25, so AND logic is also established in this AND gate 20, and the read pulse is sent to the magnetic bubble storage device 1 side. enters. i.e. transfer direction signal
DIR instructs to read data from the magnetic bubble storage device 1, input it to the RAM 2, and write it.

Conversely, when transferring and writing data from RAM2 to magnetic bubble storage device 1, the transfer direction signal DIR is L.
level, and is input to AND gates 19 and 22 via OR gate 17. Also host CPU3
From there, a read pulse is input to the AND gate 22 via the OR gate 25 via the signal line 10a. As a result, the AND logic of the AND gate 22 is established, and a read pulse is input to the RAM 2.
On the other hand, the transfer end signal TXAK is inverted by the inverter 26, becomes L level, and is input to the AND gate 19 via the OR gate 24, so AND logic is also established in this AND gate 19, and the magnetic bubble storage device 1 receives the following information. Write pulse is input. That is, based on the transfer direction signal DIR, it is instructed to read data from the RAM 2, transfer it to the magnetic bubble storage device 1, and write it.

When the transfer is completed, the transfer end signal TXAK goes to L level, is inverted to H level by inverter 26, and is inputted to each AND gate 19, 20, 21, 22 via OR gates 24, 25, and the gates are closed.

〔Effect of the invention〕

As described above, according to the present invention, a signal indicating the direction of data transfer between the magnetic bubble storage device and an external device is provided on the magnetic bubble storage device side, and this signal is sent to the R/
The configuration is such that it is input to the W pulse controller. Without this signal, DMA operation cannot be performed without using a circuit that can set the data transfer direction, such as a DMA controller. However, by using the signal according to the present invention, it is possible to simply install an additional circuit at low cost. , substantial DMA operation can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data transfer method of a conventional magnetic bubble storage device, FIG. 2 is a block diagram showing an embodiment of a data transfer method of a magnetic bubble storage device according to the present invention, and FIG. 3 is a read/write pulse. FIG. 2 is a block diagram showing an embodiment of a controller. In the figure, 1 is a magnetic bubble storage device, 2 is a magnetic bubble storage device, and 2 is a magnetic bubble storage device.
RAM, 3 is a host CPU, 9 is an R/W pulse controller, and DIR is a transfer direction signal.

Claims (1)

[Scope of Claims] 1. A magnetic bubble memory element, a writing means and a reading means for the magnetic bubble memory element, and a data transfer control means for controlling data transfer between the writing means and reading means and an external device. The apparatus further comprises a pulse signal generating means that outputs first and second pulse signals when a data transfer request signal is input, and when the data transfer control means outputs the data transfer request signal, the pulse signal generating means outputs the first and second pulse signals. 1 pulse signal is input to the data transfer control means as a data transfer response signal, and when the data transfer direction display means indicates the first state, the second pulse signal is input as a data write signal to the data transfer control means. input to the control means, and the data transfer direction display means indicates the second direction.
2. A data transfer method for a magnetic bubble storage device, wherein the second pulse signal is input to the data transfer control means as a data read signal when the state is indicated.