KR20000060513A - Interfacing apparatus - Google Patents

Abstract

PURPOSE: An interface apparatus is provided to perform DMA operation between two devices through a data bus without a memory waste when a host microprocessor is different from a data memory bus size of an external I/O device, by using a control signal generator and a bidirectional buffer. CONSTITUTION: An interface apparatus includes a first and a second bidirectional buffers(202,203), and a control signal generator(201). A host system memory and external I/O device have a different data bus size to one another. A host microprocessor(100) controls a data transmission between the host system memory and the external I/O device. The first and the second bidirectional buffers(202,203) are positioned between the host system memory and the external I/O device. The control signal generator(201) outputs a signal for controlling a direction of the first and the second bidirectional buffers(202,203) and an enable operation of the buffers. One side of the first bidirectional buffer(202) is connected to a low order bit data bus of the host system memory. One side of the second bidirectional buffer(203) is connected to a high order bit data bus of the host system memory. The other side parts of the first and second bidirectional buffers(202,203) are commonly connected to a data bus of the external I/O device(101). Thereby, the interface apparatus is provided to perform DMA operation between two devices through a data bus without a memory waste when a host microprocessor is different from a data memory bus size of an external I/O device.

Description

Interfacing apparatus

The present invention relates to an interface device that enables an interface between a host system memory having a different bus size and an external input / output device.

In general, in most systems based on host microprocessors, data transfer rates can be achieved by using programmatic methods of block transfer between memory or data transfer between memory and external input / output (I / O) devices. As a result, the microprocessor spends most of its time involved in transferring data between memory and external I / O devices.

Also, since the external I / O device responds slowly, the microprocessor must wait for polling before the external I / O device can transmit data. This is a waste of time because it must be put in a register and stored back in memory.

Therefore, in order to improve the efficiency of the system while increasing the data transfer rate, a direct memory access controller (DMAC), a second central processing unit (CPU) dedicated to data transfer, is placed in the microprocessor. It allows direct data processing between memory and memory or between external I / O devices and memory. In this case, the DMAC forms a transmission circuit (channel) independent from the microprocessor when performing data transmission in a DMA manner so that data can be directly transmitted and received between the memory and the external I / O device. The DMA refers to performing data exchange between an external I / O device and a memory directly without passing through an operation processing device such as a microprocessor. For example, it is commonly used when a block transfer of data is performed between a memory and a floppy disk device or a magnetic drum device.

At this time, if the data bus size of the host microprocessor is 32 bits and the data bus size of the external I / O device is 16 bits, transferring 32-bit data between the memory and the external I / O device using DMAC without wasting the whole memory is necessary. impossible.

1 is a block diagram illustrating a conventional system in which the host microprocessor 100 has a 32-bit data memory bus size and the external I / O device 101 has a 16-bit data bus size. Can interface only the lower 16 bits (D [0:15]) to the external I / O device 101.

That is, only D [0:15] of the host system memory 102, 103 data buses may be connected to IO_D [0:15] of the external I / O device 101. The upper 16 bits (D [15:31]) cannot be directly connected to the external I / O device 101.

For this reason, when the memory data is transferred to the external I / O device 101 by the DMA operation in the host system memories 102 and 103, the data of the upper 16 bits (D [16:31]) cannot be transferred. Therefore, when storing the data to be transmitted in the memory 102 and 103, the memory address is increased by 4 and the data must be written using only 16 bits so that only the lower 16 bits can be transmitted.

Therefore, in the conventional system, not only half of the entire host system memories 102 and 103 can be written during the DMA operation, but also the stored data and the increase in address are different, which causes various problems in the system software.

The present invention is to solve the above problems, an object of the present invention is that if the data memory bus size of the host microprocessor and the external I / O device is different, the DMA operation between the two devices over the data bus without waste of memory It is to provide an interface device to enable.

1 is a general block diagram of a host system including 32-bit host system memory and 16-bit external I / O devices.

2 is a block diagram of a host system including an interface device, a 32-bit host system memory, and a 16-bit external I / O device according to the present invention.

3 (a) to 3 (f) are operation timing diagrams of respective units in the host interface operation of FIG.

4 (a) to 4 (f) are operation timing diagrams of respective units in the DMA operation in FIG.

Explanation of symbols for main parts of the drawings

100: host microprocessor

101: external I / O device 102,103: system memory

201: control signal generator 202,203: bidirectional buffer

The interface device according to the present invention for achieving the above object is, when the data memory bus size of the host microprocessor and the external I / O device is different, that is, the data bus size of the host microprocessor is 32 bits, the external I / O If the device's data bus size is 16 bits, the data from the upper 16-bit data bus is muxed to the lower 16-bit data bus to enable 32-bit data transfer between memory and external I / O devices with DMA operation without wasting the total memory. and a control signal generator for generating a signal for controlling the bidirectional buffer and the enable and direction of the bidirectional buffer.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

2 is a block diagram of an interface device according to the present invention, in which two 16-bit two-way buffers 202 and 203 are designed between the host system memory 102 and 103 and the external I / O device 101. One side of the buffer (hereinafter referred to as the first buffer) 202 is connected to the lower 16-bit data bus D [0:15] of the host system memory 102, and the other bidirectional buffer (hereinafter referred to as first buffer). One side of the 203 is connected to the upper 16-bit data bus (D [16:31]) of the host system memory 103. In this case, the other of the first and second buffers 202 and 203 is commonly connected to the 16-bit data bus IO_D [0:15] of the external I / O device 101.

In addition, the system includes a control signal generator 201 for controlling the first and second buffers 202 and 203 to transmit memory data to the external I / O device 101 in a DMA operation in the system memories 102 and 103. Is designed. In this case, the control signal generator 201 may be designed using, for example, an electrically programmable logic device (EPLD).

The present invention configured as described above can be divided into a host interface operation and a DMA operation. That is, the host interface operation is a data transfer between the host system memory 102 and 103 and the external I / O device 101 through the host microprocessor 100, and the DMA operation is the system memory 102 and 103 and the external I / O device. The data transfer between the 101 is done without passing through the host microprocessor 100.

First, the host interface operation will be described. In the case of lower 16-bit memory data transfer, the lower 16-bit data of the system memory 102 can be transmitted to the external I / O device 101 by enabling the first buffer 202. have. At this time, the second buffer 203 is disabled.

In the case of upper 16-bit memory data transfer, the second buffer 203 is enabled, and the first buffer 202 is disabled. At this time, the upper 16-bit data of the system memory 103 is transmitted to the external I / O device 101 via the host microprocessor 100.

In the absence of normal data transfer, the first and second buffers 202 and 203 are disabled. That is, the first buffer 202 is enabled for the lower 16-bit data D [0:15], and the second buffer 203 is enabled for the upper 16-bit data D [16:31]. Let's do it. And the normal state disables both.

On the other hand, during the DMA operation, the first and second buffers 202 and 203 are alternately enabled. The direction is also appropriately adjusted as data is written to or read from the host system memories 102 and 103.

However, since the host interface uses only 16 bit data, only the first buffer 202 may always be enabled. In this case, the host microprocessor 100 must properly adjust the direction when the external I / O device 101 is read or written.

To this end, the control signal generator 201 receives a signal (CS, DACK.B_WRITE) necessary for interface control from the host microprocessor 100 and the host microprocessor 100 accesses the external I / O device 101. Signals DIR, OE1, OE2, DACK, and IO_WRITE required for controlling the first and second buffers 202 and 203 are generated. Here, CS is a chip select signal, DACK is a DMA acknowledgment signal, and B_WRITE is a data read / write signal from the host microprocessor 100.

That is, when the host microprocessor 100 reads data from the external I / O device 101 or writes data to the external I / O device 101 through the host interface, or in the DMA operation, the data of the system memory 102, 103. To the external I / O device 101 or to write the data of the external I / O device 101 to the system memory 102 and 103 according to the direction (DIR) and enable of the first and second buffers 202 and 203. Generate signals (/ OE1, / OE2).

The timing diagrams of the control signals corresponding to each case are shown in FIGS. 3 and 4.

FIG. 3 is a timing diagram of a host interface in which the host microprocessor 100 writes data to or reads data from the external I / O device 101. The first part of the host microprocessor 100 is based on a dotted line. A timing diagram when the microprocessor 100 reads the value of the register in the external I / O device 101, and the second part of the diagram shows the value of the register in the host microprocessor 100 in the register of the external I / O device 101. This is a timing chart when writing.

That is, in the first part of FIG. 3, since the host microprocessor 100 accesses 16 bits stored in the external I / O device 101, only the first buffer 202 needs to be controlled. The movement direction DIR of the data moves from the external I / O device 101 to the host system data bus as shown in FIG. The enable signal / OE1 of the first buffer 202 can be effectively used in a section in which the / CS signal of the host microprocessor 100 is valid as shown in FIG. 3A as shown in FIG. You can also set the direction to '0' with similar timing. At this time, the second buffer 203 is disabled, and the IO_WRITE signal is set to '0'.

3, only 16 bits of data are transmitted and the direction DIR of the data is from the host system data bus to the external I / O device 101 data bus. Thus, the enable signal / OE1 of the first buffer 202 is enabled at the moment / CS is enabled and the direction of data is this signal if the signal is '1' when the B_WRITE signal of the host microprocessor 100 is '1'. The IO_WRITE signal of the external I / O device 101 is made as shown in FIG. 3 (f), and the direction DIR is also set to '1'.

As described above, since the 16-bit transmission is performed in the host interface, the second buffer 203 does not need to be enabled.

4 is a timing diagram in which the host microprocessor 100 performs DMA operation with the external I / O device 101. In this case, data is transferred between the DMA controller and the memory regardless of the host microprocessor 100. Therefore, since the upper and lower 16-bit data are continuously transmitted, the first and second buffers 202 and 203 should be alternately enabled. 4 is a timing diagram when data is transmitted from the 32-bit host system memories 102 and 103 to the external I / O device 101 by 16 bits, and the rear part is an external I / O using DMA. A timing diagram when the 16-bit data of the O device 101 is transferred to the host system memories 102 and 103.

First, referring to the first part of FIG. 4, the system memories 102 and 103 are read operations and sequentially transmit data by 16 bits. In addition, the host system loads data stored in the system memories 102 and 103 on the data bus by 16 bits during the rising of the DMA acknowledgment (/ DACK) signal as shown in FIG. At this time, the external I / O device 101 usually reads data at the rising of / DACK. Since the direction of data movement is from the host system memories 102 and 103 to the external I / O device 101, the direction DIR of the first and second buffers 202 and 203 is set to '1' as shown in FIG. In this case, the enable signal causes the data enable signal / OE1 of the first buffer 202 to be '0' in FIG. 4 (d) in the first / DACK, and the second buffer (in the second / DACK). The data enable signal / OE2 of 203 is set to '0' as shown in FIG. Thus, the first and second buffers 202 and 203 are alternately enabled during the DMA transfer period.

On the contrary, in the latter part of FIG. 4, the data flow becomes the data bus of the host system memories 102 and 103 from the external I / O device 101 data bus, and the B_WRITE signal is shown in FIG. 4 because the host system memories 102 and 103 are write operations. It becomes '1' as in (b). Thus, DIR, which is the direction of the first and second buffers 202 and 203, should be '0' as shown in FIG. 4 (c), and the enable signals / OE1 and / OE2 are similarly shown in FIG. As shown in (e), the first and second buffers 202 and 203 are alternately enabled.

By doing so, 16-bit data of the external I / O device 101 is stored in the 32-bit host system memories 102 and 103 without waste.

As described above, according to the interface device according to the present invention, a 16-bit bidirectional buffer for DMA operation between a 32-bit host system memory and a 16-bit external I / O device and a signal for controlling the enable and direction of the buffer are provided. By using the control signal generator to generate, the data memory bus size of the host microprocessor and the external I / O device are different, that is, the data bus size of the host microprocessor is 32 bits and the data bus size of the external I / O device is 16 Even the bits allow DMA operation between two devices over the data bus without wasting memory.

In addition, when data transfer requests from external I / O devices can be performed simultaneously without burdening the host microprocessor, the performance of the entire system can be improved.

In addition, by using the bidirectional buffer as an interface circuit and generating only the direction control signal and the enable signal of the bidirectional buffer in the control signal generator designed by EPLD, there is an effect of minimizing the size of logic and reducing the number of gates of the required logic.

Claims (3)

In a system consisting of host system memory having different data bus sizes, external I / O devices, and host microprocessors that control the transfer of data between them, First and second bidirectional buffers disposed between the host system memory and an external I / O device; And a control signal generator for generating a signal for controlling the direction and the enable of the first and second bidirectional buffers under the control of the host microprocessor. One side of the first bidirectional buffer connects to a lower bit data bus of host system memory, one side of the second bidirectional buffer connects to an upper bit data bus of host system memory, and the other side of the first and second bidirectional buffers. Is commonly connected to the data bus of an external I / O device. The method of claim 1, wherein the control signal generator And enable only one of the first and second bidirectional buffers during a host interface operation in which data transfer between the host system memory and an external I / O device is performed through a host microprocessor. The method of claim 1, wherein the control signal generator And alternately enable the first and second bidirectional buffers during a direct memory access (DMA) operation in which data transfer between the host system memory and an external I / O device is not through a host microprocessor.