JPS6418748U - - Google Patents
Info
- Publication number
- JPS6418748U JPS6418748U JP1987114425U JP11442587U JPS6418748U JP S6418748 U JPS6418748 U JP S6418748U JP 1987114425 U JP1987114425 U JP 1987114425U JP 11442587 U JP11442587 U JP 11442587U JP S6418748 U JPS6418748 U JP S6418748U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- lead
- island
- semiconductor
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000008188 pellet Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims 4
- 238000005452 bending Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Description
第１図ａは本考案の一実施例に係る第１の半片
リードフレームの平面図、同図ｂは同図ａのＡ―
Ａ断面図、同図ｃは側面図である。第２図ａ，ｂ
，ｃはそれぞれ、第１図の半片リードフレームに
組合わされる第２の半片リードフレームの平面図
、Ａ―Ａ断面図、側面図である。第３図ａは第１
図と第２図の半片リードフレームを組立せて一体
のリードフレーム構体とした平面図、同図ｂは同
図ａのＡ―Ａ断面図、同図ｃは側面図である。第
４図は第３図の組合せ構体の樹脂封止を説明する
ための断面図、第５図ａ，ｂはそれぞれ従来のリ
ードフレーム構体を形成する半片リードフレーム
の一方および他方を示す平面図、第６図は従来の
半片リードフレームの組合せ構体を示す平面図、
第７図は本考案の他の実施例に係る半片リードフ
レームの平面図、第８図は第７図の半片リードフ
レームを２枚組合せた組合せ構体の平面図である
。
１，２，１１，１２，２１，４１，８２，８３
……ガイド、３，１３，２２，４２，８４……連
結部、４，１４，２３，４３，８５……リード部
、５，１５，２４，４４，８６……タイバー、６
，１６，２５，８７……ペレツト用アイランド、
７，１７，４５，８８……ワイヤ用アイランド、
８，１８，９，１９，９０，９１……曲げ部、３
０，７１……発光素子、５０，７３……受光素子
、７５，７６，７７，７８……位置決め用穴、２
７，４７……凹状切欠き、２８，４８……カギ状
突起、２９，４９……カギ状切欠き、８０……上
金型、８１……下金型。
FIG. 1a is a plan view of a first half-piece lead frame according to an embodiment of the present invention, and FIG.
A is a sectional view, and c is a side view. Figure 2 a, b
, c are a plan view, an AA sectional view, and a side view, respectively, of a second half lead frame combined with the half lead frame of FIG. 1. Figure 3a is the first
FIG. 2 is a plan view of an integrated lead frame structure obtained by assembling the half-piece lead frames shown in FIG. 2 and FIG. 2, FIG. FIG. 4 is a sectional view for explaining resin sealing of the combined structure of FIG. 3, and FIGS. 5a and 5b are plan views showing one and the other half of the lead frame half forming the conventional lead frame structure, respectively. FIG. 6 is a plan view showing a conventional combination structure of half-piece lead frames;
FIG. 7 is a plan view of a half-piece lead frame according to another embodiment of the present invention, and FIG. 8 is a plan view of a combination structure in which two half-piece lead frames of FIG. 7 are combined. 1, 2, 11, 12, 21, 41, 82, 83
... Guide, 3, 13, 22, 42, 84 ... Connection section, 4, 14, 23, 43, 85 ... Lead section, 5, 15, 24, 44, 86 ... Tie bar, 6
, 16, 25, 87... island for pellets,
7, 17, 45, 88...Wire island,
8, 18, 9, 19, 90, 91...Bending portion, 3
0,71...Light emitting element, 50,73...Light receiving element, 75,76,77,78...Positioning hole, 2
7, 47... Concave notch, 28, 48... Key-shaped projection, 29, 49... Key-shaped notch, 80... Upper mold, 81... Lower mold.
Claims (1)
支持されたリード部を有し、このリード部のうち
の一つのリードの先端に半導体ペレツトをマウン
トするアイランドが設けられ、かつ、前記リード
部は板厚方向に板厚の１／２だけ押出されて段差
付けがなされた第１の半片リードフレームと、こ
の第１の半片リードフレームと同様構造の第２の
半片リードフレームを用意し、さらに大きく段差
付けされた前記アイランドに送受の対となる半導
体ペレツトをマウントしたのち、前記第１と第２
の半片リードフレームを対称配置でそれぞれのリ
ード部が同一面に来るようにして一体に重ね合せ
られてなることを特徴とする半導体装置用リード
フレーム構体。 It has a lead part arranged and supported between two parallel elongated plate-shaped guides, an island for mounting a semiconductor pellet is provided at the tip of one of the lead parts, and the lead part Prepares a first half lead frame which is stepped by 1/2 of the board thickness in the board thickness direction, and a second half lead frame having the same structure as this first half lead frame, and further After mounting the semiconductor pellets, which will become a transmitting and receiving pair, on the island with a large step, the first and second semiconductor pellets are mounted.
1. A lead frame structure for a semiconductor device, comprising half lead frames stacked one on top of the other in a symmetrical arrangement with their respective lead parts on the same surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987114425U JPS6418748U (en) | 1987-07-24 | 1987-07-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987114425U JPS6418748U (en) | 1987-07-24 | 1987-07-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6418748U true JPS6418748U (en) | 1989-01-30 |
Family
ID=31355161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987114425U Pending JPS6418748U (en) | 1987-07-24 | 1987-07-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6418748U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01251649A (en) * | 1987-12-25 | 1989-10-06 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
-
1987
- 1987-07-24 JP JP1987114425U patent/JPS6418748U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01251649A (en) * | 1987-12-25 | 1989-10-06 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
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