JPS6418734U - - Google Patents
Info
- Publication number
- JPS6418734U JPS6418734U JP11280587U JP11280587U JPS6418734U JP S6418734 U JPS6418734 U JP S6418734U JP 11280587 U JP11280587 U JP 11280587U JP 11280587 U JP11280587 U JP 11280587U JP S6418734 U JPS6418734 U JP S6418734U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- chip
- die island
- utility
- model registration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図ａは本実施例の半導体装置の断面図、第
１図ｂはその平面図、第２図ａは他の実施例の半
導体装置の断面図、第２図ｂはその平面図、第３
図は従来の半導体装置の断面図である。
４……半導体装置、５……チツプ、６……フレ
ーム、７……モールド樹脂、８……フレーム、９
……網状体。
FIG. 1a is a sectional view of the semiconductor device of this embodiment, FIG. 1b is a plan view thereof, FIG. 2a is a sectional view of a semiconductor device of another embodiment, FIG. 2b is a plan view thereof, and FIG. 3
The figure is a cross-sectional view of a conventional semiconductor device. 4... Semiconductor device, 5... Chip, 6... Frame, 7... Mold resin, 8... Frame, 9
...reticular body.
Claims (1)
されたフレーム部分を樹脂封止した半導体装置に
おいて、 上記ダイアイランド部分を網状に形成したこと
を特徴とする半導体装置。 (2) 上記ダイアイランド部分に打抜き穴を設け
、該穴を覆うように網状体を取り付けて構成した
ことを特徴とする実用新案登録請求の範囲第１項
記載の半導体装置。[Claims for Utility Model Registration] (1) A semiconductor device in which a chip and a frame portion on which the chip is mounted on a die island are sealed with resin, characterized in that the die island portion is formed in a net shape. (2) The semiconductor device according to claim 1, which is a utility model registration, characterized in that a punched hole is provided in the die island portion, and a net-like body is attached to cover the hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11280587U JPS6418734U (en) | 1987-07-23 | 1987-07-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11280587U JPS6418734U (en) | 1987-07-23 | 1987-07-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6418734U true JPS6418734U (en) | 1989-01-30 |
Family
ID=31352078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11280587U Pending JPS6418734U (en) | 1987-07-23 | 1987-07-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6418734U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5814557A (en) * | 1981-07-17 | 1983-01-27 | Fujitsu Ltd | Semiconductor device |
| JPS59134857A (en) * | 1983-01-21 | 1984-08-02 | Toshiba Corp | Semiconductor device |
| JPS59159552A (en) * | 1983-03-03 | 1984-09-10 | Yamagata Nippon Denki Kk | Semiconductor device |
-
1987
- 1987-07-23 JP JP11280587U patent/JPS6418734U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5814557A (en) * | 1981-07-17 | 1983-01-27 | Fujitsu Ltd | Semiconductor device |
| JPS59134857A (en) * | 1983-01-21 | 1984-08-02 | Toshiba Corp | Semiconductor device |
| JPS59159552A (en) * | 1983-03-03 | 1984-09-10 | Yamagata Nippon Denki Kk | Semiconductor device |