JPS59159552A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59159552A
JPS59159552A JP3474783A JP3474783A JPS59159552A JP S59159552 A JPS59159552 A JP S59159552A JP 3474783 A JP3474783 A JP 3474783A JP 3474783 A JP3474783 A JP 3474783A JP S59159552 A JPS59159552 A JP S59159552A
Authority
JP
Japan
Prior art keywords
lead frame
die
laser
bonding
island
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3474783A
Other languages
Japanese (ja)
Inventor
Shoji Kobayashi
小林　昭司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP3474783A priority Critical patent/JPS59159552A/en
Publication of JPS59159552A publication Critical patent/JPS59159552A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/8322—Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/83224—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Abstract

PURPOSE:To rapidly perform die bonding with a laser by providing a plurality of small holes in an island part for die-bonding a lead frame. CONSTITUTION:A plurality of the holes 8 are provided in the island part 5 for die-bonding the lead frame 1. The frame 1 is placed on a lead frame set-up block 2 and then irradiated with the laser light 6 by means of a laser gun 3 from below. The laser light comes incident through the small holes 8 of the island part 5 and then makes a silicon die 4 fuse to the island part 5 by heating a junction auxiliary material 7 such as a solder piece.

Description

【発明の詳細な説明】 本発明は半導体装置の製造に於て、シリコンのダイを登
載し、かつ半導体装置のリード端子を形成するべき部分
とそれらの部分の補強部、わく糾みを形成するリードフ
レームの形状に関するものである。DETAILED DESCRIPTION OF THE INVENTION In manufacturing a semiconductor device, the present invention involves mounting a silicon die, and forming portions of the semiconductor device where lead terminals are to be formed, reinforcing portions for those portions, and lining. This relates to the shape of the lead frame.

半導体装置の機能部をなすシリコンダイをリードフレー
ムに固着する諸方法のうちレーザーを用いる場合、従来
は第１図の如く上部よ如レーザー６を照射し、しかる後
、早急にシリコンダイ４を押く方法、あるいは第２図の
如く、下部よりリードフレーム１の描該ダイボンディン
グを行なう島状部分（以後アイランド部と云う）５に照
射しつつシリコンダイ４を固着する方法が案出されて居
た。しかるにこれらはその熱放散の速度や熱効率の点で
劣るものでありその処理スピードに於て欠点を有してい
た。Among the various methods for fixing a silicon die, which forms a functional part of a semiconductor device, to a lead frame, when using a laser, conventionally, the upper part is irradiated with a laser 6 as shown in FIG. Alternatively, as shown in FIG. 2, a method has been devised in which the silicon die 4 is fixed while irradiating the island-shaped portion (hereinafter referred to as the island portion) 5 of the lead frame 1 from below where die bonding is to be performed. Ta. However, these are inferior in terms of heat dissipation speed and thermal efficiency, and have drawbacks in processing speed.

本発明の目的は、熱効率よく、かつ迅速にレーザーによ
るダイポンティスゲを行なえるリードフレームを提示す
ることにある。An object of the present invention is to provide a lead frame that can thermally efficiently and quickly perform diponte staking using a laser.

本発明によれば、レーザ一方式による。クイボンディン
グの利点を最大に生かした迅速なるかつ従来よシ高温溶
融材料を用いたダイボンディングを行なう事が出来る。According to the present invention, one type of laser is used. By making the most of the advantages of die bonding, it is possible to perform die bonding quickly and using high-temperature melting materials compared to conventional methods.

次に本発明を図を用いてよシ詳細に説明する。Next, the present invention will be explained in detail using the drawings.

第１図は本発明のリードフレームを用いた場合のダイボ
ンディング方法を示す一例図である。即ち、本発明によ
るアイランド部（５）に貫通する穴（８）を多数個開け
たリードフレーム（１）はリードフレームを置く為のブ
ロックの上に置かれ、下方からレーザー光（６）の照射
をレーザーガ〉′（３）より受りる。照射されたレーザ
ーはアイランド部５の小穴８を辿じ２侵入し、リードフ
レームアイランド部５と予め１−゛かれているシリコン
ダイ４裏面、若しくはシリコンダイ４とアイランドの固
着をより容易〃らしめる為のＡ、ｕ片、Ａ′田片的の接
合補助１料を同時に加熱し、瞬時にシリコンダイ４をア
イランド部５に溶着せしめる事が出来る。有］し、アイ
ランド部に１；）１けらｆまた穴１ｄ必ず１−も貫通し
７て居なくても良く検数の穴の一部あるいは全部が盲管
状をなしていてもよいもので々）る。レーザーの出力を
適度に選ぶ事により盲管状に残された部分の金属は溶解
し、更にアイランドと、シリコンダイとの溶着を向上す
る場合がある。またアイランド部の穴は単一でもよく、
また全体が網状であっても良いものとする。FIG. 1 is an example diagram showing a die bonding method using the lead frame of the present invention. That is, a lead frame (1) having a plurality of holes (8) formed through the island portion (5) according to the present invention is placed on a block for placing the lead frame, and is irradiated with laser light (6) from below. Receive from Laserga〉'(3). The irradiated laser follows the small hole 8 of the island portion 5 and enters into the lead frame island portion 5 and the back side of the silicon die 4 that has been attached in advance, or makes it easier to fix the island to the silicon die 4. The silicon die 4 can be instantaneously welded to the island portion 5 by heating the bonding aid materials A, U, and A' for the purpose at the same time. 1;) 1 hole in the island part; 1 hole 1 d does not necessarily have to pass through 7; part or all of the counting hole may be in the form of a blind tube. ). By appropriately selecting the laser output, the metal remaining in the blind tube may be melted and the welding between the island and the silicon die may be improved. Also, the hole in the island part may be single,
Further, the entire structure may be reticulated.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図は従来のリードフレームを用いた場合の
ダイボンディング時の烏敞図、第３図は本発明のり−ド
７レームを用いた場合のアイランド近傍の拡大断面［ゾ
であを。 １・・・・・・リー　トフレー　ム、２・・・・・・リ
ー　ドフレーム設置ブロック、３・・・・・・レーザー
ガン、４・・・・・・シリコンダイ、５・・・・・・リ
ードフレームアイランド部ドの固着をよシ容易ならしめ
る為の接合補助金性。 ８・・・・・・アイランド部に穴げられた穴。Figures 1 and 2 are schematic diagrams of die bonding when a conventional lead frame is used, and Figure 3 is an enlarged cross-sectional view of the vicinity of the island when the glue 7 frame of the present invention is used. of. 1...Lead frame, 2...Lead frame installation block, 3...Laser gun, 4...Silicon die, 5...・A bonding aid to make it easier to fix the lead frame island part. 8... A hole drilled in the island part.

Claims (1)

【特許請求の範囲】[Claims] ダイボンデインクを行なう位置に貫通あるいは盲管状を
なす小穴を一個から多数個開けたことを特徴とする半導
体装置。A semiconductor device characterized in that one to many small holes in the form of a through hole or a blind tube are formed at positions where die bonding is performed.
JP3474783A 1983-03-03 1983-03-03 Semiconductor device Pending JPS59159552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3474783A JPS59159552A (en) 1983-03-03 1983-03-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3474783A JPS59159552A (en) 1983-03-03 1983-03-03 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59159552A true JPS59159552A (en) 1984-09-10

Family

ID=12422914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3474783A Pending JPS59159552A (en) 1983-03-03 1983-03-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59159552A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6418734U (en) * 1987-07-23 1989-01-30
EP0758145A3 (en) * 1995-08-08 1997-11-19 Taiyo Yuden Co., Ltd. Method of manufacturing circuit module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6418734U (en) * 1987-07-23 1989-01-30
EP0758145A3 (en) * 1995-08-08 1997-11-19 Taiyo Yuden Co., Ltd. Method of manufacturing circuit module

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