JPH03187234A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03187234A JPH03187234A JP32624589A JP32624589A JPH03187234A JP H03187234 A JPH03187234 A JP H03187234A JP 32624589 A JP32624589 A JP 32624589A JP 32624589 A JP32624589 A JP 32624589A JP H03187234 A JPH03187234 A JP H03187234A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- semiconductor chip
- area
- optical semiconductor
- plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 229910000679 solder Inorganic materials 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000002844 melting Methods 0.000 claims abstract description 3
- 230000008018 melting Effects 0.000 claims abstract description 3
- 238000005476 soldering Methods 0.000 claims description 13
- 239000000853 adhesive Substances 0.000 claims description 11
- 230000001070 adhesive effect Effects 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims 1
- 230000003287 optical effect Effects 0.000 abstract description 24
- 238000005201 scrubbing Methods 0.000 abstract description 8
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は光半導体チップのはんだ付方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for soldering optical semiconductor chips.
第２図は従来の半導体チップのはんだ付方法を示す模式
断面図であり、第２図（ａ）において、（１）は光半導
体チップ、（２＋は板状はんだ、（３）ははんｔご表面
の酸化膜（太絆部”） 、 （４）は接着部である。板
状はんだ（２）の面積が光半導体チ、ツブ（１）の被接
着面の面積に比べてやや大きいことが特徴である。FIG. 2 is a schematic cross-sectional view showing a conventional method for soldering semiconductor chips. In FIG. 2(a), (1) is an optical semiconductor chip, (2+ is plate-shaped solder, and (3) is solder t The oxide film (thick bond part) on the surface (4) is the adhesive part.The area of the plate-shaped solder (2) is slightly larger than the area of the adhered surface of the optical semiconductor chip and tube (1). is a feature.
次に、第２図６）により従来のはんだ付方法について説
明する。Next, a conventional soldering method will be explained with reference to FIG. 2 (6).
図中、第２図（ａ）と同一符号は同一のものを示す。In the figure, the same reference numerals as in FIG. 2(a) indicate the same parts.
板状はんだ（２）を光半導体チップ（１）と接着部（４
）の間に挾み、全体をはんだ融点以上に熱し、光半導体
チップ（１）上方に一定時間力を加えることによりはん
だをつぶし、その後全体をはんだ！＠点よりも充分低い
湿度にまで冷却しはんだ付けを終了する。The solder plate (2) is attached to the optical semiconductor chip (1) and the adhesive part (4).
), heat the whole to above the melting point of the solder, crush the solder by applying force above the optical semiconductor chip (1) for a certain period of time, and then solder the whole! Cool down to a sufficiently lower humidity than point @ and complete soldering.
一般に光半導体チップの大きさは２５０〜５００戸口で
厚みが１００〜２００ ｐｒｒ＋ 程度と極いて小さ
く、はんだ付けの段階でスクラブ（チ、ツブをはんだ番
こ押し付は左右にこすりつけること）を行うことは困難
で、こいため、スクラブなしい状態ではＡｕＳｎをはじ
めとして大部分のはんだ材において、光半導体チップ上
方から力を加えてはんだをつぶすｔごけでは、はんだ表
面に存在する酸化膜のだい１ζ接着強度がほとんどとれ
ないという問題点力Ｓある。Generally, the size of an optical semiconductor chip is extremely small, about 250 to 500 mm and the thickness is about 100 to 200 prr+, so scrubbing (rubbing left and right to press the solder bumps) is required at the soldering stage. It is difficult and difficult to do this without scrubbing, so when using most solder materials, including AuSn, applying force from above the optical semiconductor chip to crush the solder will destroy the oxide film on the solder surface. There is a problem that the 1ζ adhesive strength is almost impossible.
例えば、はんｔご付は後に光半導体チップに横方向から
力を加えると、Ｏグラムから数１０グラムで光半導体チ
ップが外れることが多い（実用上中くとも１００グラム
以上の接着強度が必要である。）などの問題点かあ−た
。For example, when a soldering iron is later applied to the optical semiconductor chip from the side, the optical semiconductor chip often comes off within 0 to several tens of grams (for practical purposes, adhesive strength of at least 100 grams is required). ) and other problems.
本発明は上記のような問題点を解決するためになされた
もので、スクラブなしに光半導体チップ接着強度が充分
とれる半導体装置の製造方法を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can ensure sufficient adhesion strength to an optical semiconductor chip without scrubbing.
本発明に係る半導体装置の製造方法は、板状はんだの面
積を光半導体チップの被接着面の面積に比べて充分小さ
くするようにしたものである。In the method for manufacturing a semiconductor device according to the present invention, the area of the plate-shaped solder is made sufficiently smaller than the area of the surface to be bonded of the optical semiconductor chip.
本発明における板状はんだの面積は、光半導体チップ被
接着面積より充分小さくされているので、板状はんだが
光半導体チップによりつぶされるとき、はんだ面積が小
さいた力、酸化膜におおわれていない新しいはんｔごが
飛び出し、これが光半導体チップと接着部の間に満たさ
れる。The area of the plate-shaped solder in the present invention is made sufficiently smaller than the area to which the optical semiconductor chip is adhered, so that when the plate-shaped solder is crushed by the optical semiconductor chip, the solder area is small and the area of the solder plate is sufficiently smaller than the area to which the optical semiconductor chip is attached. The tungsten pops out and fills the gap between the optical semiconductor chip and the bonding part.
以下、本発明の一実施例を図について説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
＠１図は本発明の一実施例を示す模式断面図であり、Ｉ
ｉ１図（ａ）において、（１）は光半導体チップ、（２
）は板状はんだ、（３）ははんだ表面の酸化膜（太線部
）、（４）は接着部である。板状はんだ（２１の面積が
光半導体チップ（１）の被接着面の面積に比べて充分小
さいことが特徴である。@1 Figure is a schematic sectional view showing one embodiment of the present invention, and I
i1 In Figure (a), (1) is an optical semiconductor chip, (2
) is a plate-shaped solder, (3) is an oxide film on the solder surface (bold line part), and (4) is an adhesive part. A feature is that the area of the plate-shaped solder (21) is sufficiently smaller than the area of the surface to be bonded of the optical semiconductor chip (1).
なお、はんだ付けＶ手順は第２図（ｂ）に示すように従
来のものの場合と全く同様である。Incidentally, the soldering V procedure is exactly the same as that of the conventional method, as shown in FIG. 2(b).
本発明の実施例では板状はんだ（２）例えばＡｕＳｎが
光半導体チップ（１）によりつぶされるとき、はんだ面
積が小さいため、酸化膜（３）におおわれていない新し
いはんだが飛び出し、酸化膜（３）は寸断される。この
ため、新しいはんだが光半導体チップ（１；と接着部の
すき間に充満し、スクラブなしに充分な接着強度（少く
とも１００グラム以上）が得られる。In the embodiment of the present invention, when the plate-shaped solder (2), for example, AuSn, is crushed by the optical semiconductor chip (1), new solder that is not covered with the oxide film (3) jumps out because the solder area is small. ) is shredded. Therefore, new solder fills the gap between the optical semiconductor chip (1;) and the adhesive portion, and sufficient adhesive strength (at least 100 grams or more) can be obtained without scrubbing.
なお、上記実施例ではＡｕ Ｓｎ はんｒごの場合に
ついて説明したが、本発明による方法は他のあらゆるは
んだに対しても有効である、
また、半導体チップ（１）として光半導体小ような微小
チップの場合について述べたが、光半導体に限らず、他
の半導体チップまたは半導体以外の他の物体に対しても
本発明による方法は有効である。Although the above embodiment describes the case of Au Sn solder, the method according to the present invention is also effective for all other types of solder. Although the case of chips has been described, the method according to the present invention is effective not only for optical semiconductors but also for other semiconductor chips or other objects other than semiconductors.
以上のように本発明によれば、スクラブするのと同様、
酸化膜のない状態で半導体チップのはんだ付けができる
ので、充分な接着強度を得ることができ、また、スクラ
ブなしではんだ付けができることから、はんだ付けのプ
ロセスを自動化することも容易となる。As described above, according to the present invention, like scrubbing,
Since semiconductor chips can be soldered without an oxide film, sufficient adhesive strength can be obtained, and since soldering can be performed without scrubbing, it is easy to automate the soldering process.
第１図は本発明によるはんだ付けの一実施例を示す模式
断面図、第２図は従来のはんだ付方法を示す模式断面図
である。
図において、（１）は光半導体チップ、（２１は板状は
んだ、（３）は酸化膜、（４）は接着部を示す。
なお、図中、同一符号は同一 または相当部分を示す。
第１図
第２図FIG. 1 is a schematic sectional view showing an embodiment of soldering according to the present invention, and FIG. 2 is a schematic sectional view showing a conventional soldering method. In the figure, (1) is an optical semiconductor chip, (21 is a plate-shaped solder, (3) is an oxide film, and (4) is an adhesive part. In the figures, the same reference numerals indicate the same or equivalent parts. Figure 1 Figure 2
Claims (1)
接着面の面積に比べて面積が充分に小さい板状はんだを
半導体チップと接着部の間に挾み、半導体チップ、はん
だ、接着部をはんだ融点以上に熱して半導体チップ上部
に力を加えることにより、半導体チップをはんだ付けす
ることを特徴とする半導体装置の製造方法。When soldering semiconductor chips, a plate-shaped solder whose area is sufficiently small compared to the area of the surface to be bonded of the semiconductor chip is sandwiched between the semiconductor chip and the adhesive part, and the semiconductor chip, solder, and adhesive part are heated to a temperature above the melting point of the solder. A method for manufacturing a semiconductor device, characterized by soldering a semiconductor chip by heating and applying force to the top of the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32624589A JPH03187234A (en) | 1989-12-16 | 1989-12-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32624589A JPH03187234A (en) | 1989-12-16 | 1989-12-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03187234A true JPH03187234A (en) | 1991-08-15 |
Family
ID=18185617
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32624589A Pending JPH03187234A (en) | 1989-12-16 | 1989-12-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03187234A (en) |
-
1989
- 1989-12-16 JP JP32624589A patent/JPH03187234A/en active Pending
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