JPH01209736A - Method of replacing semiconductor element - Google Patents
Method of replacing semiconductor elementInfo
- Publication number
- JPH01209736A JPH01209736A JP3590988A JP3590988A JPH01209736A JP H01209736 A JPH01209736 A JP H01209736A JP 3590988 A JP3590988 A JP 3590988A JP 3590988 A JP3590988 A JP 3590988A JP H01209736 A JPH01209736 A JP H01209736A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor element
- solder
- thin film
- silicon plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims description 18
- 229910000679 solder Inorganic materials 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 24
- 239000010409 thin film Substances 0.000 claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 238000003825 pressing Methods 0.000 claims description 7
- 239000010931 gold Substances 0.000 abstract description 12
- 230000002950 deficient Effects 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 239000010408 film Substances 0.000 abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052737 gold Inorganic materials 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000006096 absorbing agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/799—Apparatus for disconnecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子の交換方法に関し、特に半田バンプ
を有するフリップチップ型半導体素子の交換方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for replacing a semiconductor device, and more particularly to a method for replacing a flip-chip type semiconductor device having solder bumps.
最近、半導体装置の軽薄短小化に伴い半導体素子の実装
方法も高密度化が要求されるようになり、その一つの方
法としてフリップチップ接続技術が広く普及する傾向に
ある。Recently, as semiconductor devices have become lighter, thinner, shorter, and smaller, there has been a demand for higher density mounting methods for semiconductor elements, and flip-chip bonding technology is becoming more widespread as one of these methods.
第3図(a)、(b)はそれぞれかかる−船釣なフリッ
プチップ接続技術を説明するための工程順に示す素子実
装基板の断面図である。FIGS. 3(a) and 3(b) are cross-sectional views of an element-mounted substrate shown in the order of steps for explaining such a simple flip-chip connection technique.
第3図(a)、(b)に示すように、それぞれ(a)は
実装前、(b)は実装後の状態を表わし、バンプ2を有
するフリップチップ型半導体素子11をフェイスダウン
で基板1上に搭載し、半田バンプ2を溶融して半導体素
子11と基板1との接続をとるものである。As shown in FIGS. 3(a) and 3(b), FIG. 3(a) shows the state before mounting, and FIG. 3(b) shows the state after mounting. The semiconductor element 11 and the substrate 1 are connected by melting the solder bumps 2.
このようにして接続が終了した後の半導体装置は一般に
選別検査あるいはバーンインテストによって良否判定が
おこなわれ、良品は樹脂コート等の次工程にすすめられ
るが、選別検査あるいはバーンインテストで不良となっ
た半導体装置は不良半導体素子の交換が困難であるため
、大部分は不良廃棄されている。After the connection is completed in this way, semiconductor devices are generally judged to be good or bad by a sorting inspection or burn-in test, and non-defective devices are sent to the next process such as resin coating. Most devices are discarded because it is difficult to replace defective semiconductor elements.
上述した従来の半導体素子の不良品廃棄の理由および解
決課題を第4図を参照して説明する。The reasons for discarding the above-mentioned conventional semiconductor devices with defective products and the problems to be solved will be explained with reference to FIG.
第4図(a)〜(C)は従来の一例を説明するための工
程順に示した半導体装置の断面図である。FIGS. 4A to 4C are cross-sectional views of a semiconductor device shown in the order of steps to explain a conventional example.
まず、第4図(a)に示すように、基板1と被交換用半
導体素子3とは半田バンプ2を介して接続されているな
め、基板1または半導体素子3を加熱すれば半田バンプ
2を溶融させることができる。次に、溶融している時に
、かかる半導体素子3を機械的に引き上げてやれば基板
1と半導体素子3とを分離させることができる。First, as shown in FIG. 4(a), the substrate 1 and the semiconductor element 3 to be replaced are connected through the solder bumps 2, so if the substrate 1 or the semiconductor element 3 is heated, the solder bumps 2 are removed. Can be melted. Next, by mechanically pulling up the semiconductor element 3 while it is melted, the substrate 1 and the semiconductor element 3 can be separated.
次に、第4図(b)に示すように、かかる半導体素子3
の分離において、半田バンプ2は半導体素子3にパン1
2′として残るほかに基板1上にも不規則に残存半田5
が残存する。尚、この基板1上の残存半田5は直径10
0〜200μmと微細であるので、プリント板の修理等
につかわれる網状の吸い取り器あるいは吸引式の半田吸
い取り器ではほとんど除去することができない。Next, as shown in FIG. 4(b), such a semiconductor element 3
In the separation, the solder bump 2 is attached to the semiconductor element 3 by the solder bump 1.
In addition to remaining as solder 2', irregularly remaining solder 5 also exists on the board 1.
remains. Note that the remaining solder 5 on this substrate 1 has a diameter of 10
Since the solder particles are as fine as 0 to 200 μm, they can hardly be removed using a net-like solder absorber or a suction-type solder absorber used for repairing printed circuit boards.
次に、第4図(C)に示すように、新しい半田バンプ2
を有する新しい交換用半導体素子9をフェイスダウンで
基板1上に搭載するにあたっては、不規則に残存する基
板1上の残存半田5の高さにばらつきがあるため、半導
体素子9上の半田バンプ2と基板1上の残存半田5とが
すべてにおいては接触せず、基板1あるいは半導体素子
9を加熱しても溶融接続できない接続不良点が発生する
ことが多い。Next, as shown in FIG. 4(C), a new solder bump 2 is
When mounting a new replacement semiconductor element 9 face down on the substrate 1, the solder bumps 2 on the semiconductor element 9 may The remaining solder 5 on the substrate 1 does not come into contact with each other at all points, and poor connection points often occur where melting and connection cannot be achieved even if the substrate 1 or the semiconductor element 9 is heated.
従って、交換した新しい半導体素子9も接続不良のため
に良品とはならず、再び不良廃棄せざるを得ない、この
ため、交換の歩留、ひいては製造歩留が著しく低下し、
半導体装置としての製造コスト高および信頼性の低下を
招くという欠点を有している。Therefore, the new semiconductor element 9 that has been replaced is not a good product due to poor connection, and has to be discarded again.As a result, the replacement yield and, by extension, the manufacturing yield are significantly reduced.
This has the disadvantage of increasing manufacturing costs and decreasing reliability as a semiconductor device.
本発明の目的は、かかる不良半導体素子等の被交換半導
体素子を容易に交換でき且つ信頼性を向上させた半導体
素子の交換方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for replacing a semiconductor element, in which a semiconductor element to be replaced, such as a defective semiconductor element, can be easily replaced and reliability is improved.
本発明の半導体素子の交換方法は、基板あるいは半導体
素子を加熱してこの半導体素子を基板から離脱させる工
程と、半田ぬれ性のよい薄膜を形成したシリコン板の前
記薄膜を前記基板に対向させて前記基板上の前記半導体
素子搭載位置に押しあてる工程と、前記シリコン板ある
いは前記基板を加熱して前記基板上に残存する半田を前
記シリコン板上の前記薄膜に吸収させる工程と、しかる
後交換する新たな半田バンプを有する半導体素子を前記
基板上に搭載して接続する工程とを含んで構成される。The method for replacing a semiconductor element of the present invention includes the steps of heating a substrate or a semiconductor element to separate the semiconductor element from the substrate, and placing the thin film of a silicon plate on which a thin film with good solder wettability is formed to face the substrate. A step of pressing the semiconductor element onto the semiconductor element mounting position on the substrate, a step of heating the silicon plate or the substrate to absorb the solder remaining on the substrate into the thin film on the silicon plate, and then exchanging the solder. The method includes a step of mounting and connecting a semiconductor element having new solder bumps onto the substrate.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)〜(e)は本発明の第一の実施例を説明す
るための工程順に示した半導体装置の断面図である。FIGS. 1(a) to 1(e) are cross-sectional views of a semiconductor device shown in order of steps for explaining a first embodiment of the present invention.
まず、第1図(a)に示すように、基板1上に被着され
ている不良の半導体素子、すなわち被交換用半導体素子
3を基板1上より離脱させるにあたっては、ホットプレ
ート4上に不良半導体素子3を搭載した基板1をのせ加
熱する。次に、共晶半田の場合には200℃〜230℃
で半田バンプ2が溶融するので、例えばビンセット等を
使って半導体素子3を基板1から離脱させる。First, as shown in FIG. 1(a), in order to remove the defective semiconductor element adhered on the substrate 1, that is, the semiconductor element 3 to be replaced, from the substrate 1, the defective semiconductor element on the hot plate 4 must be removed. A substrate 1 on which a semiconductor element 3 is mounted is placed and heated. Next, in the case of eutectic solder, 200℃ to 230℃
Since the solder bumps 2 are melted, the semiconductor element 3 is removed from the substrate 1 using, for example, a bottle set.
次に、第1図(b)に示すように、基板1上から半導体
素子3を離脱させると、その後に残存半田5が不揃いで
残る。Next, as shown in FIG. 1(b), when the semiconductor element 3 is removed from the substrate 1, residual solder 5 remains in an irregular manner.
次に、第1図(c)に示すように、金薄膜(以下Au膜
と記す)7を形成したシリコン板6を押しあて治具8に
より荷重数g〜数10gで基板1上の残存半田5が残っ
ている半導体素子3の搭載位置に押しあてる。ここでシ
リコン板6は半導体素子3の基材となるシリコンウェー
ハから切り出したもの或いはシリコンウェーハそのもの
であり、平面度がよいため基板1の面と良好に接触する
。またAu膜7は厚さが100〜10000オングスト
ロームであり、通常の蒸着ないしスパッタ法によりあら
かじめシリコン板6上に形成されたものである。続いて
、シリコン板6を押しあてた状態で加熱する。加熱方法
は、第1図(a)において説明したように、200〜2
30℃に設定されたホットプレート上で行なっても良い
し、或いは押しあて治具8にヒータ機構をもたせ押しあ
て治具8によりシリコン板6を加熱してもよいし、また
両者の併用でもよい。かかるAu薄膜7は半田に対する
ぬれ性がよく且つシリコン板6は平坦性がよいため基板
1上の残存半田5はきわめて良好にシリコン板上のAu
膜7に吸収される。尚、半田の活性化を促進するために
、第1図(c)において基板1とシリコン板6との間に
フラックスを介在させてもよい。Next, as shown in FIG. 1(c), the silicon plate 6 on which the gold thin film (hereinafter referred to as Au film) 7 has been formed is pressed against the remaining solder on the substrate 1 using a pressing jig 8 under a load of several grams to several tens of grams. 5 is pressed against the mounting position of the remaining semiconductor element 3. Here, the silicon plate 6 is cut out from a silicon wafer, which is the base material of the semiconductor element 3, or is a silicon wafer itself, and has good flatness so that it makes good contact with the surface of the substrate 1. The Au film 7 has a thickness of 100 to 10,000 angstroms, and is previously formed on the silicon plate 6 by a normal vapor deposition or sputtering method. Subsequently, the silicon plate 6 is heated while being pressed against it. As explained in FIG. 1(a), the heating method is as follows:
This may be carried out on a hot plate set at 30° C., or the pressing jig 8 may be equipped with a heater mechanism and the silicon plate 6 may be heated by the pressing jig 8, or both may be used in combination. . Since the Au thin film 7 has good solder wettability and the silicon plate 6 has good flatness, the remaining solder 5 on the substrate 1 is very well bonded to the Au on the silicon plate.
It is absorbed into the membrane 7. Incidentally, in order to promote solder activation, flux may be interposed between the substrate 1 and the silicon plate 6 in FIG. 1(c).
次に、第1図(d)に示すように、押しあて治具8を取
除くと、基板1上に残存した半田5を大部分は半田5″
としてAu膜に吸収し、わずかな量が半田5′として基
板1上に残されるが、基板1表面はほとんど平滑化され
た状態になる。Next, as shown in FIG. 1(d), when the pressing jig 8 is removed, most of the remaining solder 5 on the board 1 is removed by the solder 5''.
Although a small amount is left on the substrate 1 as solder 5', the surface of the substrate 1 is almost smoothed.
次に、第1図(e)に示すように、新たな交換用半導体
素子9を基板1上に搭載し、残存半田5′上に半田バン
ブ2を介して接続する。この半田バンプ2の溶融接続に
は通常のりフロ一方法(例えば赤外線リフロー法、ホッ
トプレート法等)が用いられる。Next, as shown in FIG. 1(e), a new replacement semiconductor element 9 is mounted on the substrate 1 and connected to the remaining solder 5' via the solder bumps 2. A normal adhesive flow method (eg, infrared reflow method, hot plate method, etc.) is used to melt and connect the solder bumps 2.
かかる上述の手順を終ることにより、半田バンブ2を有
するフリップチップ型半導体素子3と9との交換が完成
する。By completing the above-described procedure, the replacement of the flip-chip semiconductor elements 3 and 9 having the solder bumps 2 is completed.
第2図は本発明の第二の実施例を説明するための半導体
装置の断面図である。FIG. 2 is a sectional view of a semiconductor device for explaining a second embodiment of the present invention.
第2図に示すように、この第二の実施例が前述した第一
の実施例に比べて異なる点は、不良半導体素子3を基板
1より離脱させる際にこの半導体素子3のみを局所的に
加熱することである。例えば、不良半導体素子3の上方
に熱風発生器10を設置し、半導体素子3の上面に熱風
をふきつけて200〜230℃に加熱する。本実施例の
交換方法は、基板1上に複数個のフリップチップ型半導
体素子を搭載する場合に特に有効である。即ち、交換す
る必要のない良品の半導体素子には熱履歴を与えること
なく、不良半導体素子3のみを交換できるからである。As shown in FIG. 2, the difference between this second embodiment and the first embodiment described above is that when the defective semiconductor element 3 is removed from the substrate 1, only this semiconductor element 3 is locally removed. It means heating. For example, a hot air generator 10 is installed above the defective semiconductor element 3, and hot air is blown onto the upper surface of the semiconductor element 3 to heat it to 200 to 230°C. The replacement method of this embodiment is particularly effective when a plurality of flip-chip semiconductor elements are mounted on the substrate 1. That is, only the defective semiconductor element 3 can be replaced without imparting thermal history to good semiconductor elements that do not need to be replaced.
尚、上述の実施例では半田ぬれ性のよい薄膜に金薄膜を
例にとって説明したが、他にスズ、ニッケル、場合によ
っては半田等も可能である。In the above-mentioned embodiments, a gold thin film is used as an example of a thin film having good solder wettability, but other materials such as tin, nickel, and possibly solder may also be used.
以上説明したように、本発明の半導体素子の交換方法は
被交換用半導体素子を離脱せしめた後の基板に残る残存
半田の高さをほぼ均一にせしめ且つ半田ぬれ性のよい薄
膜を用いることにより、フリップチップ型半導体素子の
交換が容易に歩留よく行えるため、半導体装置の製造歩
留をあげ且つ製造コストを下げられる上、信頼性も向上
させることができるという効果がある。As explained above, the semiconductor element replacement method of the present invention makes the height of the residual solder remaining on the substrate almost uniform after the semiconductor element to be replaced is removed, and uses a thin film with good solder wettability. Since the flip-chip type semiconductor element can be easily replaced with a high yield, there is an effect that the manufacturing yield of the semiconductor device can be increased, the manufacturing cost can be lowered, and the reliability can also be improved.
第1図(a)〜(e)は本発明の第一の実施例を説明す
るための工程順に示した半導体装置の断面図、第2図は
本発明の第二の実施例を説明するための半導体装置の断
面図、第3図(a)。
(b)はそれぞれ−船釣なフリップチップ接続技術を説
明するための工程順に示す素子実装基板の断面図、第4
図(a)〜(c)は従来の一例を説明するための工程順
に示した半導体装置の断面図である。
1・・・基板、2・・・半田バンプ、3・・・被交換用
半導体素子、4・・・ホットプレート、5・・・残存半
田、6・・・シリコン板、7・・・金薄膜、8・・・押
しあて治具、9・・・交換用半導体素子、10・・・熱
風発生器。1(a) to (e) are cross-sectional views of a semiconductor device shown in the order of steps for explaining a first embodiment of the present invention, and FIG. 2 is a sectional view for explaining a second embodiment of the present invention. FIG. 3(a) is a cross-sectional view of the semiconductor device of FIG. (b) is a cross-sectional view of an element mounting board shown in the order of steps to explain the flip-chip connection technology;
Figures (a) to (c) are cross-sectional views of a semiconductor device shown in order of steps to explain a conventional example. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Solder bump, 3... Semiconductor element to be replaced, 4... Hot plate, 5... Residual solder, 6... Silicon plate, 7... Gold thin film , 8... Pressing jig, 9... Replacement semiconductor element, 10... Hot air generator.
Claims (1)
交換方法において、前記基板あるいは半導体素子を加熱
して前記半導体素子を前記基板から脱離させる工程と、
半田ぬれ性のよい薄膜を形成したシリコン板の前記薄膜
を前記基板に対向させて前記基板上の前記半導体素子搭
載位置に押しあてる工程と、前記シリコン板あるいは前
記基板を加熱して前記基板上に残存する半田を前記シリ
コン板上の前記薄膜に吸収させる工程と、しかる後交換
する新たな半田バンプを有する半導体素子を前記基板上
に搭載して接続する工程とを含むことを特徴とする半導
体素子の交換方法。In a method for replacing a semiconductor element melt-connected on a substrate using solder bumps, the step of heating the substrate or the semiconductor element to detach the semiconductor element from the substrate;
a step of pressing the thin film of a silicon plate on which a thin film with good solderability is formed, facing the substrate and against the semiconductor element mounting position on the substrate; and heating the silicon plate or the substrate to place the thin film on the substrate. A semiconductor device comprising the steps of absorbing remaining solder into the thin film on the silicon plate, and then mounting and connecting a semiconductor device having new solder bumps to be replaced on the substrate. How to replace.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3590988A JPH01209736A (en) | 1988-02-17 | 1988-02-17 | Method of replacing semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3590988A JPH01209736A (en) | 1988-02-17 | 1988-02-17 | Method of replacing semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01209736A true JPH01209736A (en) | 1989-08-23 |
Family
ID=12455157
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3590988A Pending JPH01209736A (en) | 1988-02-17 | 1988-02-17 | Method of replacing semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01209736A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5391501A (en) * | 1992-11-12 | 1995-02-21 | Hitachi, Ltd. | Method for manufacturing integrated circuits with a step for replacing defective circuit elements |
EP0714123A2 (en) | 1994-11-22 | 1996-05-29 | Sharp Kabushiki Kaisha | A semiconductor device, a semiconductor device-mounted apparatus, and a method for replacing the semiconductor device |
US5550083A (en) * | 1992-09-21 | 1996-08-27 | Fujitsu Limited | Process of wirebond pad repair and reuse |
US6062460A (en) * | 1996-11-27 | 2000-05-16 | Sharp Kabushiki Kaisha | Apparatus for producing an electronic circuit |
CN108040436A (en) * | 2017-12-08 | 2018-05-15 | 郑州云海信息技术有限公司 | A kind of asymmetric IC pads steel mesh of PCBA and its design method |
US20220310551A1 (en) * | 2021-03-24 | 2022-09-29 | Samsung Electronics Co., Ltd. | Semiconductor manufacturing apparatus |
-
1988
- 1988-02-17 JP JP3590988A patent/JPH01209736A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5550083A (en) * | 1992-09-21 | 1996-08-27 | Fujitsu Limited | Process of wirebond pad repair and reuse |
US5391501A (en) * | 1992-11-12 | 1995-02-21 | Hitachi, Ltd. | Method for manufacturing integrated circuits with a step for replacing defective circuit elements |
EP0714123A2 (en) | 1994-11-22 | 1996-05-29 | Sharp Kabushiki Kaisha | A semiconductor device, a semiconductor device-mounted apparatus, and a method for replacing the semiconductor device |
US5726501A (en) * | 1994-11-22 | 1998-03-10 | Sharp Kabushiki Kaisha | Semiconductor device having a solder drawing layer |
US6062460A (en) * | 1996-11-27 | 2000-05-16 | Sharp Kabushiki Kaisha | Apparatus for producing an electronic circuit |
CN108040436A (en) * | 2017-12-08 | 2018-05-15 | 郑州云海信息技术有限公司 | A kind of asymmetric IC pads steel mesh of PCBA and its design method |
US20220310551A1 (en) * | 2021-03-24 | 2022-09-29 | Samsung Electronics Co., Ltd. | Semiconductor manufacturing apparatus |
US11658147B2 (en) * | 2021-03-24 | 2023-05-23 | Samsung Electronics Co., Ltd. | Semiconductor manufacturing apparatus |
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