JP2910398B2 - Solder bump formation method - Google Patents

Solder bump formation method

Info

Publication number
JP2910398B2
JP2910398B2 JP4102572A JP10257292A JP2910398B2 JP 2910398 B2 JP2910398 B2 JP 2910398B2 JP 4102572 A JP4102572 A JP 4102572A JP 10257292 A JP10257292 A JP 10257292A JP 2910398 B2 JP2910398 B2 JP 2910398B2
Authority
JP
Japan
Prior art keywords
solder
substrate
forming
pieces
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4102572A
Other languages
Japanese (ja)
Other versions
JPH0669640A (en
Inventor
喜一 吉野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP4102572A priority Critical patent/JP2910398B2/en
Publication of JPH0669640A publication Critical patent/JPH0669640A/en
Application granted granted Critical
Publication of JP2910398B2 publication Critical patent/JP2910398B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3478Applying solder preforms; Transferring prefabricated solder patterns

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半田バンプ形成方法、特
に、半導体素子実装用の半田バンプ形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a solder bump, and more particularly to a method for forming a solder bump for mounting a semiconductor device.

【0002】[0002]

【従来の技術】従来より、半導体素子のフリップチップ
実装などで必要な半田バンプの形成方法としては、メッ
キや蒸着で半田を供給する技術がある。
2. Description of the Related Art Conventionally, as a method of forming solder bumps required for flip chip mounting of semiconductor elements, there is a technique of supplying solder by plating or vapor deposition.

【0003】図4(a)〜(d)は、メッキ法で半導体
素子上に半田バンプを形成する方法を示す工程断面図で
ある。まず、シリコン基板11上に配線層15、保護層
10が形成されたLSI9の全面にスパッタなどでCr
等の接着層17、Ni等の拡散防止層16順次積層す
る。〔図4(a)〕次いで、レジスト層20を全面に塗
布し露光、現像して電極部分のレジスト層20を除去す
る。その後、メッキにより厚い半田層19を電極部に形
成する。〔図4(b)〕メッキ後は、レジスト層20を
除去し半田層19をマスクとして電極部以外の拡散防止
層16、接着層17をエッチング除去し、半田供給工程
が完了する。〔図4(c)〕蒸着で半田を供給する場
合、接着層、拡散防止層は、レジスト層を形成して電極
部以外を予め除去しておき、メッキに代わる蒸着工程で
は、電極部のみ穴を明けた金属板を取付け、電極部のみ
に半田層を形成する。 通常、LSI上の半田層19は
加熱溶融され球面状の半田バンプ12に成形される。
〔図4(d)〕 図5(a),(b)は特願平02ー178854で提案
した、金属シートをポンチ、ダイスを用いて所定の径と
厚みで打ち抜き、ポンチを使って直接電極上に金属片を
圧着する方法を示す。基板7上の所定の位置にポンチ1
とダイス3を位置ぎめする。金属シート2をポンチ1で
打ち抜き、打ち抜かれた金属片18をポンチ1先端で基
板7上へ圧着する。この方法は、半田供給にも応用でき
る。
FIGS. 4A to 4D are process sectional views showing a method of forming a solder bump on a semiconductor element by a plating method. First, Cr is formed by sputtering or the like on the entire surface of the LSI 9 on which the wiring layer 15 and the protective layer 10 are formed on the silicon substrate 11.
And a diffusion preventing layer 16 of Ni or the like. [FIG. 4A] Next, a resist layer 20 is applied to the entire surface, exposed and developed to remove the resist layer 20 at the electrode portion. Thereafter, a thick solder layer 19 is formed on the electrode portion by plating. [FIG. 4 (b)] After plating, the resist layer 20 is removed, and the diffusion preventing layer 16 and the adhesive layer 17 other than the electrode portion are removed by etching using the solder layer 19 as a mask, thereby completing the solder supply step. [FIG. 4 (c)] When solder is supplied by vapor deposition, the adhesive layer and the diffusion preventing layer are formed by forming a resist layer and removing portions other than the electrode portion in advance, and in the vapor deposition process instead of plating, only the electrode portion has holes. Then, a soldered layer is formed only on the electrode part. Usually, the solder layer 19 on the LSI is heated and melted and formed into the spherical solder bump 12.
[FIG. 4 (d)] FIGS. 5 (a) and 5 (b) show a metal sheet punched out with a predetermined diameter and thickness using a punch and a die proposed in Japanese Patent Application No. 02-178854, and a direct electrode is formed using a punch. The method of crimping a metal piece is shown above. Punch 1 at predetermined position on substrate 7
And die 3 are positioned. The metal sheet 2 is punched with the punch 1, and the punched metal piece 18 is pressed onto the substrate 7 at the tip of the punch 1. This method can also be applied to solder supply.

【0004】[0004]

【発明が解決しようとする課題】上述したような従来の
半田バンプ形成方法は以下のような問題点があった。す
なわち、メッキ法や蒸着法は、工程が複雑であること、
大きい膜厚の半田層を付けるには処理処理時間が長くな
ること、このため、バンプ形成コストが高くなること、
大きな設備投資が必要であることなどの問題があった。
さらに、これらの方法では、組成のずれが起き易く信頼
性の高い半田を得にくいこと、半導体素子などでは歩留
を低下させる要因となること、ウエハー状態で処理する
必要があり柔軟性にかけるなどの問題もある。またメッ
キ法では均一な膜を得にくいので形状の均一なバンプを
得られないといった問題もある。半田シートをポンチ、
ダイスで打ち抜き、打ち抜き用ポンチを使って半田片を
直接圧着する方法は、上述のような欠点がないが、電極
部に半田の打ち抜き片を加圧して供給するので、表面層
が機械的強度が弱い半導体素子の場合ポンチ加圧力の高
度の制御が必要となる。また、半田と電極との接着力を
得るには、半田と合金化しやすいAuなどを電極表面に
つけ、基板加熱を行う必要があり、Auの半田中への拡
散など信頼性上の問題があった。
The conventional solder bump forming method as described above has the following problems. That is, the plating method and the vapor deposition method require complicated processes,
In order to attach a solder layer having a large thickness, the processing time becomes longer, and therefore, the bump formation cost becomes higher,
There were problems such as the need for large capital investment.
Furthermore, in these methods, it is difficult to obtain a highly reliable solder due to a composition deviation easily, it is a factor that lowers the yield in semiconductor devices, etc., and it is necessary to process in a wafer state, so that flexibility is required. There is also a problem. Further, there is another problem that it is difficult to obtain a uniform film by the plating method, so that a bump having a uniform shape cannot be obtained. Punch the solder sheet,
The method of punching with a die and directly pressing the solder pieces using a punch for punching does not have the disadvantages described above.However, since the punched pieces of solder are supplied to the electrodes by pressing, the surface layer has a mechanical strength. In the case of a weak semiconductor device, it is necessary to control the altitude of the pressing force of the punch. In addition, in order to obtain an adhesive force between the solder and the electrode, it is necessary to apply Au or the like, which easily alloys with the solder, to the surface of the electrode and to heat the substrate, which has a problem in reliability such as diffusion of Au into the solder. .

【0005】[0005]

【課題を解決するための手段】本発明の半田バンプ形成
方法は、プレス加工して形成した半田片を基板の電極の
配置を反転した配置で仮配置板上に配置した後、仮配置
板と基板とを重ね合わせて配置された半田片と電極とを
接触させ、半田片を仮配置板から基板の電極に転写する
方法である。ここで、半田片を仮配置板から基板の電極
に転写した後、基板を加熱することにより、転写された
半田片を溶融して球面形状にするとともに電極に接着さ
せてもよい。本発明のもう一つの半田バンプ形成方法
は、プレス加工して形成した半田片を基板の電極の配置
を反転した配置で仮配置板上に配置した後、仮配置板と
基板とを重ね合わせ配置された半田片と電極を接触さ
せ、次いで基板を加熱することにより配置した半田片を
仮配置板から基板の電極に転写すると同時に溶融せしめ
て球面形状にするとともに電極に接着させる方法であ
る。仮配置板への半田片の配置は、シート状半田材料を
打ち抜き加工して形成した半田片を打ち抜き加工に用い
たポンチを使って直接仮配置板に押し付ける、または仮
配置板上に落とすことにより行う。
According to the solder bump forming method of the present invention, a solder piece formed by pressing is placed on a temporary placement plate in an arrangement in which the arrangement of electrodes on a substrate is inverted, and then the solder piece is formed. This is a method in which a solder piece and an electrode, which are arranged by overlapping a substrate, are brought into contact with each other, and the solder piece is transferred from the temporary arrangement plate to an electrode of the substrate. Here, after the solder pieces are transferred from the temporary arrangement plate to the electrodes of the substrate, the transferred solder pieces may be melted into a spherical shape and adhered to the electrodes by heating the substrate. Another method of forming a solder bump of the present invention is to arrange a solder piece formed by press working on a temporary placement board in an arrangement in which the arrangement of electrodes on a board is inverted, and then place the temporary placement board and the board on top of each other. In this method, the solder pieces are brought into contact with the electrodes, and then the solder pieces are transferred from the temporary placement plate to the electrodes of the substrate by heating the substrate and simultaneously melted to form a spherical shape and adhere to the electrodes. Solder pieces are placed on the temporary placement board by pressing the solder pieces formed by punching the sheet-like solder material directly onto the temporary placement board using the punch used for the punching process, or by dropping on the temporary placement board Do.

【0006】[0006]

【実施例】次に本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0007】図1(a)〜(e)は、本発明の実施例1
の工程図である。まず、ダイシングなどで用いられる加
熱により接着層が発泡し接着力が低下する加熱発泡剥離
シート13をガラス板5上に張り付け、仮配置板21と
した。〔図1(a)〕次いで、150μm厚の錫鉛の半田
シート14を200μm径のポンチ1、ダイス3により打
ち抜き、半田片4をポンチ1により直接加熱発泡剥離シ
ート13上に押し付けることにより、仮配置板21上に
半田片4を並べた。半田片4の配置は、LSI9の電極
配置を反転した配置にしておく必要がある。〔図1
(b)〕次いで、フラックス5を約7μm回転塗布機で
塗布したLSI9上に、LSI9の電極8と半田片4の
位置が一致するよう仮配置板21を位置合わせしながら
LSI電極8上に載せ、低加圧で押し付けながら仮配置
板21を100 ℃に加熱した。〔図1(c)〕次いで、仮
配置板21を引き上げると、半田片4は仮配置板21か
ら離れ、LSI電極8に転写される。〔図1(d)〕こ
の後、LSI9を200℃に加熱して半田片4を溶融し球
面形状の半田バンプ12にした。〔図1(e)〕仮配置
板21の加熱発泡剥離シートは100℃加熱により粘着性
を失ったのに対しフラックスには粘着性があるので、L
SI電極8への転写が可能となる。上記のポンチ1、ダ
イス3を用いて直接電極上に半田片4をのせる場合、電
極表面層はAuのような半田と接着しやすい金属である
必要があり、またポンチ1の加圧力は40g以上にする必
要であったが、本発明の場合、Ni、Cu等の表面層で
あってもよく、しかも1電極当たりの押し付け力は約3
gでも良好な転写ができた。また、LSIに塗布するフ
ラックス5は、転写後の溶融時に半田および電極の酸化
層を除去する働きを兼ねることができるが、厚すぎると
半田片が流れ出し、ブリッジや1つの電極に半田が集ま
る不良が起きやすく、一方、薄すぎると溶融時の還元作
用が不足しバンプ形状が悪くなる。フラックスの厚さと
しては半田材料の4〜50パーセントが適当であった。
FIGS. 1A to 1E show a first embodiment of the present invention.
FIG. First, a heated foam release sheet 13 in which an adhesive layer foams due to heating used in dicing or the like and the adhesive strength is reduced is stuck on the glass plate 5 to form a temporary arrangement plate 21. [FIG. 1 (a)] Next, a tin-lead solder sheet 14 having a thickness of 150 μm is punched out with a punch 1 and a die 3 having a diameter of 200 μm, and a solder piece 4 is directly pressed by a punch 1 onto a heat-foaming peeling sheet 13, thereby temporarily. The solder pieces 4 were arranged on the arrangement plate 21. The arrangement of the solder pieces 4 needs to be an inverted arrangement of the electrodes of the LSI 9. [Figure 1
(B)] Next, on the LSI 9 on which the flux 5 is applied by a spin coater of about 7 μm, the temporary placement plate 21 is placed on the LSI electrode 8 while the positions of the electrodes 8 of the LSI 9 and the solder pieces 4 are aligned. The temporary placement plate 21 was heated to 100.degree. C. while pressing with low pressure. [FIG. 1C] Next, when the temporary placement plate 21 is pulled up, the solder pieces 4 are separated from the temporary placement plate 21 and transferred to the LSI electrodes 8. [FIG. 1 (d)] Thereafter, the LSI 9 was heated to 200 ° C. to melt the solder pieces 4 to form spherical solder bumps 12. [FIG. 1 (e)] The heat-foamed peeling sheet of the temporary placement plate 21 loses its tackiness by heating at 100 ° C., whereas the flux has tackiness.
Transfer to the SI electrode 8 becomes possible. When the solder piece 4 is directly placed on the electrode by using the punch 1 and the die 3, the electrode surface layer needs to be made of a metal such as Au which is easy to adhere to the solder, and the pressing force of the punch 1 is 40 g. However, in the case of the present invention, a surface layer of Ni, Cu or the like may be used, and the pressing force per electrode is about 3
Good transfer was also possible with g. Further, the flux 5 applied to the LSI can also function to remove the solder and the oxide layer of the electrode at the time of melting after the transfer. On the other hand, if it is too thin, the reducing action at the time of melting is insufficient, and the bump shape becomes poor. A suitable flux thickness was 4 to 50 percent of the solder material.

【0008】図2(a)〜(c)は、本発明の実施例2
を示す工程断面図である。実施例1と同様に仮配置板2
1として加熱発泡剥離シートを張ったガラス板を用い半
田片4を並べた。本実施例では、LSI9には電極上に
のみスクリーン印刷でフラックス7を形成した。〔図2
(a)〕次いでLSI9の電極8と半田片4の位置が一
致するよう仮配置板21を位置合わせして載せ、低加圧
を加えながら仮配置板21を100℃に加熱した。〔図2
(b)〕次いで、仮配置板21を引き上げると、半田片
4は仮配置板21から離れ、LSI電極8に転写され
る。この後、LSI9を200℃に加熱して半田片4を溶
融し球面形状の半田バンプ12にした。〔図2(c)〕
この場合、電極のみにフラックスが形成されているの
で、溶融時の半田片の流れだしなどによる不良がよりい
っそう発生しにくい。
FIGS. 2A to 2C show a second embodiment of the present invention.
FIG. Temporary arrangement plate 2 as in the first embodiment
As No. 1, solder pieces 4 were arranged using a glass plate on which a heat-foamed release sheet was stretched. In this embodiment, the flux 7 is formed on the LSI 9 only by screen printing on the electrodes. [Figure 2
(A)] Next, the temporary arrangement plate 21 was positioned and mounted so that the position of the electrode 8 of the LSI 9 and the position of the solder piece 4 coincided with each other, and the temporary arrangement plate 21 was heated to 100 ° C. while applying low pressure. [Figure 2
(B)] Next, when the temporary placement plate 21 is pulled up, the solder pieces 4 are separated from the temporary placement plate 21 and transferred to the LSI electrodes 8. Thereafter, the LSI 9 was heated to 200 ° C. to melt the solder pieces 4 to form spherical solder bumps 12. [FIG. 2 (c)]
In this case, since the flux is formed only on the electrodes, defects due to the flow of the solder pieces at the time of melting are less likely to occur.

【0009】なお、実施例1,2ではガラス板5の表面
に張り付けるシートとして加熱発泡剥離シートを用いた
が、紫外線の光照射で接着性が低下するUV硬化型シー
トであってもよい。実施例のように基板と重ね合わせて
から接着性低下のための処理をする場合、仮配置板21
の基材はガラス板5のような照射光を通す材料にする必
要がある。また実施例1、2では、基板9と重ね合わせ
てから接着性を低下させる処理をしたが、半田片4を仮
配置板21に配置した直後に処理をしてから基板9を重
ね合わせてもよい。
In the first and second embodiments, a heat-foamable release sheet is used as a sheet to be adhered to the surface of the glass plate 5, but a UV-curable sheet whose adhesiveness is reduced by irradiation with ultraviolet light may be used. In the case where a process for reducing the adhesiveness is performed after being superimposed on the substrate as in the embodiment, the provisionally arranged plate 21 is used.
The base material needs to be made of a material such as a glass plate 5 that transmits irradiation light. Further, in the first and second embodiments, the process of reducing the adhesiveness after overlapping with the substrate 9 was performed. However, the process may be performed immediately after the solder pieces 4 are arranged on the temporary arrangement plate 21 and then the substrate 9 may be overlapped. Good.

【0010】図3(a)〜(d)は、本発明の実施例3
を示す工程断面図である。本実施例では仮配置板21と
してフラックス5を塗布したガラス板5を使用した。
〔図3(a)〕半田片4をポンチ1とダイス3を用いて
配置する。次いでLSI9を100℃に加熱し、仮配置板
21をLSI9に位置ぎめして載せ、LSI9及び仮配
置板21を加熱し半田片4を電極上に溶着させた。〔図
3(c)〕この後、仮配置板21を半田溶融中に引き上
げ球形状の半田バンプ12を得た。〔図3(d)〕本実
施例の場合、仮配置板21をLSI9へ位置決めしたま
ま半田片を溶融するので、加熱時は半田バンプ12がつ
ぶれないようにガラス板5下面と電極8との距離を一定
に保持するのが望ましい。尚、本実施例の仮配置板21
として表面が細かい凹凸状態である半田とは馴染まい材
質の平板を用いても良い。この場合、半田片は表面の凹
凸により仮固定されており、半田溶融時には仮配置板2
1に溶着することはない。
FIGS. 3A to 3D show a third embodiment of the present invention.
FIG. In this embodiment, the glass plate 5 coated with the flux 5 is used as the temporary arrangement plate 21.
[FIG. 3 (a)] A solder piece 4 is arranged using a punch 1 and a die 3. Next, the LSI 9 was heated to 100 ° C., and the temporary arrangement plate 21 was positioned and mounted on the LSI 9, and the LSI 9 and the temporary arrangement plate 21 were heated to weld the solder pieces 4 on the electrodes. [FIG. 3 (c)] Thereafter, the temporary placement plate 21 was pulled up while the solder was being melted, and the spherical solder bumps 12 were obtained. [FIG. 3 (d)] In the case of the present embodiment, the solder pieces are melted while the temporary placement plate 21 is positioned on the LSI 9, so that the lower surface of the glass plate 5 and the electrode 8 are heated so that the solder bumps 12 do not collapse during heating. It is desirable to keep the distance constant. In addition, the temporary arrangement plate 21 of the present embodiment
Alternatively, a flat plate made of a material compatible with solder having a finely uneven surface may be used. In this case, the solder pieces are temporarily fixed by unevenness on the surface, and when the solder is melted, the temporary placement plate 2
1 does not weld.

【0011】本発明の方法では、プレス打ち抜きにより
半田片を形成するので、その供給量の均一性は良好であ
り、溶融後のバンプ高さは、150±2μmであった。この
ようにして得られた高精度なLSI電極上の半田バンプ
は大型で、高密度に配列された電極を持つLSIのフリ
ップチップ実装に適している。以上のように本発明の方
法を用いることにより、高密度に配列されたLSI電極
上に半田バンプを従来に比べ高精度、低コストでしかも
機械的衝撃を加えることなく形成することができる。
尚、本発明に用いる半田は、錫鉛半田のみではなく、金
錫半田、インジウム系半田、錫系半田、金シリコン半
田、金ゲルマニウム半田等にも適用できる。また本発明
は、LSIだけでなく機械的衝撃に弱い配線基板のバン
プ形成にも適用する。
In the method of the present invention, since the solder piece is formed by press punching, the uniformity of the supplied amount is good, and the bump height after melting is 150 ± 2 μm. The solder bumps on the high-precision LSI electrodes thus obtained are large and suitable for flip-chip mounting of LSIs having electrodes arranged at high density. As described above, by using the method of the present invention, solder bumps can be formed on LSI electrodes arranged at high density with higher precision, lower cost and less mechanical impact than conventional ones.
The solder used in the present invention can be applied not only to tin-lead solder but also to gold-tin solder, indium-based solder, tin-based solder, gold-silicon solder, gold-germanium solder and the like. Further, the present invention is applied not only to the LSI but also to the formation of bumps on a wiring board which is vulnerable to mechanical shock.

【0012】[0012]

【発明の効果】以上説明したように本発明は、プレス法
で形成した半田片を仮配置板に供給してから転写する方
法であるので、均一な体積の半田バンプを比較的容易に
基板に機械的負荷をかけることなく形成できるという効
果がある。また、湿式工程や真空工程が不要であり工程
が簡略であるとともに、供給する半田材料、電極構造に
対しての制約が少なく、信頼性の高い接合を得やすいと
いう利点がある。
As described above, the present invention is a method of transferring a solder piece formed by a press method to a temporary arrangement plate and then transferring the same, so that a solder bump having a uniform volume can be relatively easily formed on a substrate. There is an effect that it can be formed without applying a mechanical load. In addition, there is an advantage that a wet process or a vacuum process is not required, the process is simplified, and there is little restriction on a supplied solder material and an electrode structure, so that highly reliable bonding can be easily obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(e)は本発明の第1の実施例の工程
断面図である。
FIGS. 1A to 1E are process cross-sectional views of a first embodiment of the present invention.

【図2】(a)〜(c)は本発明の第2の実施例の工程
断面図である。
FIGS. 2A to 2C are process cross-sectional views of a second embodiment of the present invention.

【図3】(a)〜(d)は本発明の第3の実施例の工程
断面図である。
FIGS. 3A to 3D are process cross-sectional views of a third embodiment of the present invention.

【図4】(a)〜(d)は従来のメッキ法による半田バ
ンプ形成方法を示す工程断面図である。
FIGS. 4A to 4D are process cross-sectional views showing a conventional solder bump forming method by a plating method.

【図5】(a),(b)は従来のポンチとダイスを用い
た打ち抜き法による半田供給方法を示す工程断面図であ
る。
FIGS. 5A and 5B are process cross-sectional views showing a conventional solder supply method by a punching method using a punch and a die.

【符号の説明】[Explanation of symbols]

1 ポンチ 2 金属シート 3 ダイス 4 半田片 5 ガラス板 6 フラックス 7 基板 8 電極 9 LSI 10 保護層 11 シリコン基板 12 半田バンプ 13 加熱発泡剥離シート 14 半田シート 15 配線層 16 拡散防止層 17 接着層 18 金属片 19 半田層 20 レジスト層 21 仮配置板 DESCRIPTION OF SYMBOLS 1 Punch 2 Metal sheet 3 Dice 4 Solder piece 5 Glass plate 6 Flux 7 Substrate 8 Electrode 9 LSI 10 Protective layer 11 Silicon substrate 12 Solder bump 13 Heated foam peeling sheet 14 Solder sheet 15 Wiring layer 16 Diffusion prevention layer 17 Adhesive layer 18 Metal Piece 19 Solder layer 20 Resist layer 21 Temporary placement board

Claims (11)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 プレス加工して形成した半田片をポンチ
先端から基板の電極の配置を反転した配置で仮配置板上
接着層を介して順次配置した後、前記仮配置板と前記
基板とを重ね合わせて前記配置された半田片と前記電極
とを接触させ、前記配置した半田片を前記仮配置板の前
記接着層から剥離し前記基板の電極に転写することを特
徴とする半田バンプ形成方法。
1. A punch is formed by pressing a solder piece formed by press working.
After sequentially arranging the electrodes of the substrate from the tip in an inverted arrangement on the temporary arrangement plate via an adhesive layer , the temporary arrangement plate and the substrate are overlapped with each other, and the arranged solder pieces and the electrodes are arranged. Contact and place the placed solder pieces in front of the temporary placement plate
A method for forming a solder bump, wherein the method is separated from the adhesive layer and transferred to an electrode of the substrate.
【請求項2】 半田片を仮配置板から基板の電極に転写
した後、前記基板を加熱し前記転写された半田片を溶融
して球面形状にするとともに前記電極に接着させる請求
項1記載の半田バンプ形成方法。
2. The method according to claim 1, wherein after transferring the solder pieces from the temporary arrangement plate to the electrodes of the substrate, the substrate is heated to melt the transferred solder pieces into a spherical shape and adhere to the electrodes. Solder bump formation method.
【請求項3】 プレス加工して形成した半田片をポンチ
先端から基板の電極の配置を反転した配置で平板状の
配置板上に順次配置した後、仮配置板と基板とを重ね合
わせて配置された半田片と電極とを接触させ、次いで基
板を加熱することにより配置した半田片を仮配置板から
基板の電極に転写すると同時に溶融して球面形状にする
とともに電極に接着させることを特徴とする半田バンプ
形成方法。
3. A punch is formed by pressing a solder piece formed by press working.
After sequentially arranging the electrodes of the substrate from the tip on the flat temporary arrangement plate in an inverted arrangement, the solder pieces arranged on the temporary arrangement plate and the substrate are brought into contact with the electrodes, and then the substrate is contacted. A method for forming a solder bump, wherein a solder piece arranged by heating is transferred from a temporary arrangement plate to an electrode of a substrate, and simultaneously melted to form a spherical shape and adhere to the electrode.
【請求項4】 シート状半田材料を打ち抜き加工して形
成した半田片を前記打ち抜き加工に用いたポンチを使っ
て直接仮配置板に押し付ける、あるいは仮配置板上に落
とすことにより配置する請求項1〜3記載の半田バンプ
形成方法。
4. A solder piece formed by punching a sheet-like solder material is pressed directly onto a temporary placement plate using a punch used for the punching process, or dropped on the temporary placement plate. 4. The method for forming a solder bump according to any one of items 3 to 3.
【請求項5】 仮配置板の表面層が加熱により接着性が
低下する層よりなり、半田片を配置した後、基板への転
写と同時またはそれ以前に加熱処理を行う工程を有する
請求項1〜4記載の半田バンプ形成方法。
5. The method according to claim 1, wherein the surface layer of the temporary placement plate is made of a layer whose adhesiveness is reduced by heating, and has a step of performing a heat treatment simultaneously with or before the transfer to the substrate after the solder pieces are placed. 5. The method for forming a solder bump according to any one of claims 4 to 4.
【請求項6】 仮配置板の表面層が光照射により接着性
が低下する層よりなり、半田片を配置した後、基板への
転写と同時またはそれ以前に光照射を行う工程を有する
請求項1〜4記載の半田バンプ形成方法。
6. The method according to claim 1, wherein the surface layer of the temporary placement plate is made of a layer whose adhesiveness is reduced by light irradiation, and has a step of irradiating with light before or simultaneously with transfer to the substrate after arranging the solder pieces. A method for forming a solder bump according to any one of claims 1 to 4.
【請求項7】 仮配置板の表面が細かい凹凸状態である
請求項3記載の半田バンプ形成方法。
7. The method for forming a solder bump according to claim 3 , wherein the surface of the temporary placement plate is in a fine uneven state .
【請求項8】 表面にフラックスを塗布した基板に半田
片を転写する請求項1〜7記載の半田バンプ形成方法。
8. The solder bump forming method according to claim 1, wherein the solder pieces are transferred to a substrate having a surface coated with a flux.
【請求項9】 フラックスの塗布が半田片が転写される
電極部のみに行われる請求項8記載の半田バンプ形成方
法。
9. The method according to claim 8, wherein the application of the flux is performed only to the electrode portion to which the solder piece is transferred.
【請求項10】 半田片の材料が、錫系半田、錫鉛半
田、金錫半田、インジウム系半田、金シリコン半田、金
ゲルマニウム半田の中のいずれかの半田である請求項1
〜9記載の半田バンプ形成方法。
10. The solder piece material is any one of tin-based solder, tin-lead solder, gold-tin solder, indium-based solder, gold-silicon solder, and gold-germanium solder.
10. A method for forming a solder bump according to any one of claims 9 to 9.
【請求項11】 形成された半田バンプが半導体素子の
接続に適用される請求項1〜10記載の半田バンプ形成
方法。
11. The solder bump forming method according to claim 1, wherein the formed solder bump is applied to connection of a semiconductor element.
JP4102572A 1992-04-22 1992-04-22 Solder bump formation method Expired - Lifetime JP2910398B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4102572A JP2910398B2 (en) 1992-04-22 1992-04-22 Solder bump formation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4102572A JP2910398B2 (en) 1992-04-22 1992-04-22 Solder bump formation method

Publications (2)

Publication Number Publication Date
JPH0669640A JPH0669640A (en) 1994-03-11
JP2910398B2 true JP2910398B2 (en) 1999-06-23

Family

ID=14330946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4102572A Expired - Lifetime JP2910398B2 (en) 1992-04-22 1992-04-22 Solder bump formation method

Country Status (1)

Country Link
JP (1) JP2910398B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3250496B2 (en) * 1997-09-19 2002-01-28 日本電気株式会社 Optical device mounting board
JPH0828583B2 (en) * 1992-12-23 1996-03-21 インターナショナル・ビジネス・マシーンズ・コーポレイション Multilayer printed circuit board, manufacturing method thereof, and ball dispenser
US5735452A (en) * 1996-06-17 1998-04-07 International Business Machines Corporation Ball grid array by partitioned lamination process
KR101022912B1 (en) * 2008-11-28 2011-03-17 삼성전기주식회사 A printed circuit board comprising a metal bump and a method of manufacturing the same

Also Published As

Publication number Publication date
JPH0669640A (en) 1994-03-11

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