JPH03218645A - Mounting of semiconductor device - Google Patents
Mounting of semiconductor deviceInfo
- Publication number
- JPH03218645A JPH03218645A JP1401990A JP1401990A JPH03218645A JP H03218645 A JPH03218645 A JP H03218645A JP 1401990 A JP1401990 A JP 1401990A JP 1401990 A JP1401990 A JP 1401990A JP H03218645 A JPH03218645 A JP H03218645A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- semiconductor device
- solder
- electrodes
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 229910000679 solder Inorganic materials 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 29
- 230000004907 flux Effects 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 238000002844 melting Methods 0.000 claims abstract description 11
- 230000008018 melting Effects 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 3
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 abstract description 10
- 239000010409 thin film Substances 0.000 abstract description 10
- 235000011187 glycerol Nutrition 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 abstract description 3
- 239000007790 solid phase Substances 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 2
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 239000000155 melt Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3494—Heating methods for reflowing of solder
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体チップなどの半導体装置をフリップチ
ップボンデイングの手法によって配線基板上に実装する
半導体装置の実装方法に関する．従来の技術
第３図は、従来の半導体装置の実装方法の各工程を示す
断面図である．
この実装方法は、半導体チツプ１の電極に形成された半
田バンプ２を介して、一般的なフリ・ノプチップボンデ
ィングの手法により半導体チツプ１を配線基板３上に実
装する方法であって、まず第１の工程では、電極パツド
４を有し表面にフラツクス５を塗布した配線基板３に対
して、第３図（１）に示すように半導体チップ１が対向
配置され、これらの間が仮圧着される．すなわち、半導
体チツブ１は、その各半田バンプ２が対応する電極４と
対向し合うように位置合わせ装置であるフリツプチップ
ホルダーを用いて配線基板３上に位置合わせされ、フラ
ックス５の粘着力によって半田バンプ２と配線基板３側
の電極４とが仮接着される．第２の工程では，上述した
ように半導体チップ１を仮接着した配線基板３が加熱手
段であるリフロー炉に送られ、ここで第３図（２）に示
すように半田バンプ２は溶融されて配線基板３の［［ｉ
４に固着される。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for mounting a semiconductor device, such as a semiconductor chip, on a wiring board using a flip-chip bonding technique. BACKGROUND ART FIG. 3 is a cross-sectional view showing each step of a conventional semiconductor device mounting method. In this mounting method, a semiconductor chip 1 is mounted on a wiring board 3 by a general free-knop chip bonding method via solder bumps 2 formed on electrodes of a semiconductor chip 1. In the first step, as shown in FIG. 3(1), the semiconductor chip 1 is placed facing the wiring board 3 having the electrode pads 4 and coated with the flux 5 on the surface, and the space between them is temporarily pressed. It will be done. That is, the semiconductor chip 1 is aligned on the wiring board 3 using a flip chip holder, which is an alignment device, so that each solder bump 2 faces the corresponding electrode 4, and the adhesive force of the flux 5 The solder bump 2 and the electrode 4 on the wiring board 3 side are temporarily bonded. In the second step, the wiring board 3 on which the semiconductor chip 1 is temporarily bonded as described above is sent to a reflow oven, which is a heating means, where the solder bumps 2 are melted as shown in FIG. 3(2). [[i
Fixed to 4.
第３の工程では、上記工程によって互いに接続された半
導体チップ１および配線基板３がアセトンやアルコール
などの溶液で洗浄され、これによって第３図（３）に示
すようにフラックス５が除去される．
発明が解決しようとする課題
しかし、上述した従来の実装方法では、半田バンプ２を
溶融加熱するりフロー条件によっては、その後の溶液一
洗浄によってもブラックス５を完全には除去できない場
合が多く、第３図（３）に示すように半導体チップ１や
配線基板３の表面にフラックス残滓６が付着したまま残
る．その結果、フラックス残滓６のために装置の電気的
特性や信頼性が低下するという問題点を有する．また、
上述した溶液洗浄時に超音波を用いれば、フラックス残
滓６はかなりの程度まで低減できるけれども、この場合
には超音波のために半導体チップ１に特性劣化が起こり
易くなるという新たな問題が生じる．
したがって本発明の目的は、フラックス残滓に起因する
装置の特性劣化を起こすことがなく、簡単な工程で実装
できる半導体装置の実装方法を提供することである。In the third step, the semiconductor chip 1 and the wiring board 3 that have been connected to each other in the above steps are cleaned with a solution such as acetone or alcohol, thereby removing the flux 5 as shown in FIG. 3(3). Problems to be Solved by the Invention However, in the conventional mounting method described above, depending on the melting and heating of the solder bumps 2 or the flow conditions, it is often not possible to completely remove the blacks 5 even with subsequent cleaning with a solution. As shown in FIG. 3 (3), flux residue 6 remains attached to the surfaces of the semiconductor chip 1 and wiring board 3. As a result, there is a problem in that the electrical characteristics and reliability of the device deteriorate due to the flux residue 6. Also,
Although the flux residue 6 can be reduced to a considerable extent by using ultrasonic waves during the solution cleaning described above, in this case, a new problem arises in that the characteristics of the semiconductor chip 1 are more likely to deteriorate due to the ultrasonic waves. Therefore, an object of the present invention is to provide a method for mounting a semiconductor device that can be mounted in a simple process without causing deterioration of the characteristics of the device due to flux residue.
課題を解決するための手段
本発明は、半導体装置の電極に形成された半田バンプを
配線基板に形成された対応する電極に突き合わせ、半田
バンプを加熱溶融させることによって配線基板に対して
半導体装置を電気的に接続する半導体装置の実装方法に
おいて、
配線基板の各電極上に親半田金属膜を形成する工程と、
半導体装置を前記配線基板に対向させて配置し、半導体
装置の半田バンプを配線基板の対応する電極に突き合わ
せた状態で半田の融点よりも低い温度で加熱および加圧
することによって、前記金属膜を介して半田バンプと配
線基板の電極との間をフラックスを用いないで仮接着す
る工程と、互いに仮接着された状態の半導体装置および
配線基板を、半田の融点以上の温度の液体中に浸漬して
半田バンプを溶融固着させる工程とを含むことを特徴と
する半導体装置の実装方法である．作 用
本発明に従えば、フラックスを用いることなく配線基板
への半導体装置の実装が可能であり、したがってフラッ
クス残滓のために装置の電気的特性や信頼性を損なうこ
とがなく、またフラックス除去工程が不要なため工程が
簡略になる．実施例
第１図は、本発明の一実施例である半導体装置の実装方
法を示す工程図である。Means for Solving the Problems The present invention abuts a solder bump formed on an electrode of a semiconductor device against a corresponding electrode formed on a wiring board, and heats and melts the solder bump, thereby attaching the semiconductor device to the wiring board. A method for mounting a semiconductor device for electrical connection includes the steps of: forming a parent solder metal film on each electrode of a wiring board; arranging a semiconductor device to face the wiring board; and placing solder bumps of the semiconductor device on the wiring board. Temporary bonding between the solder bump and the electrode of the wiring board via the metal film without using flux by heating and pressurizing the solder bump at a temperature lower than the melting point of the solder while the solder bump is butted against the corresponding electrode of the wiring board. and a step of immersing the semiconductor device and the wiring board, which are temporarily bonded together, in a liquid at a temperature higher than the melting point of the solder to melt and fix the solder bumps. be. Effects According to the present invention, it is possible to mount a semiconductor device on a wiring board without using flux, and therefore the electrical characteristics and reliability of the device are not impaired due to flux residue, and the flux removal step is not required. The process is simplified because there is no need for Embodiment FIG. 1 is a process diagram showing a method for mounting a semiconductor device according to an embodiment of the present invention.
この実装方法は、半導体チップ１１の電極に形成された
半田バンプ１２を介して、フリップチップボンディング
の手法により半導体チップ１１を配線基板１３上に実装
する方法であって、まず第１の工程では第１図（１）に
示すように配線基板１３の表面の電極バッド１４上に低
融点金属であるインジウムからなる厚さが約３０００人
の金属薄膜１５が形成される。In this mounting method, a semiconductor chip 11 is mounted on a wiring board 13 by a flip-chip bonding method via solder bumps 12 formed on electrodes of a semiconductor chip 11. As shown in FIG. 1 (1), a metal thin film 15 made of indium, which is a low melting point metal, and having a thickness of approximately 3000 nm is formed on the electrode pad 14 on the surface of the wiring board 13.
第２の工程では、上記配線基板１３に対して半導体チッ
プ１１が対向して配置され、これらの間が仮圧着される
。すなわち、半導体チツブ１１は、その各半田バンプ１
２が配線基板１３の対応する電極１４と対向し合うよう
に、配線基板１３上に第１図（２》に示すように位置合
わせされる．第３の工程では、上記工程によって半導体
チツブ１１の位置合わせが行われた配線基板１３が半田
の融点よりもやや低い１６０〜１７０℃の温度で加熱さ
れる。これによって電極１４上の金属薄膜１５と半田バ
ンプ１２との間に若干の固相拡散が起こり、金属薄膜ｌ
５を介して半田バンプ１１と電極１４の間、つまり半導
体チツプ１１と配線基板１３との間が第１図（３》に示
すように仮接着される．
第４の工程では、半導体チップ１１を仮接着した配線基
板１３が半田の融点以上の約２５０℃の温度のグリセリ
ン液の浴槽中に約３０秒間浸漬される．これによって半
田バンプ１２が溶融し、電極１４に固着する．このあと
、メタノール溶液中で配線基板１３に付着したグリセリ
ンが洗浄除去され、最終的に第１図（４）に示すように
配線基板１３上に半導体チツプ１１が実装される．第２
図は、本発明の他の実施例である半導体装置の実装方法
を示す工程図である．
この実装方法では、まず第１の工程で配線基板１３の電
極１４に金を材料とする厚みが１０００人の金属薄膜１
５ａが第２図（１）に示すように堆積して形成される．
次の第２の工程では、先の実施例と同様に配線基板１３
上に半導体チップ１１が第２図（２》に示すように位置
合わせされる．
第３の工程では、配線基板１３を１６０〜１７０℃の温
度に加熱した状態のもとで、半導体チツプ１１が配線基
板１３に押し付けられる．その押付け圧力、は、１つの
半田バンプ１２に対して２〜３ｇ程度の力がかかる大き
さとされる．これによって電極１４上の金属薄膜１５ａ
と半田バンプ１２との間に若干の固相拡散が起こり、金
属薄膜１５ａを介して半田バンプ１１と電極１４の間、
つまり半導体チップ１１と配線基板１３との間が、第２
図《３》に示すように仮接着される．第４の工程では、
半導体チップ１１を仮接着した配線基板１３が、先の実
施例と同様に約２５０℃の温度のグリセリン液の浴槽中
に約３０秒間浸漬される．これによって半田バンプ１２
が溶融し、電極１４に固着する．最後に配線基板１３を
メタノール溶液中で洗浄することによって、配線基板１
３に付着していたグリセリンが除去され、第２図（４）
に示すように配線基板１３上に半導体チップ１１が実装
される．
発明の効果
以上のように本発明の半導体装置の実装方法によれば、
フラックスを用いないで、配線基板の電極上に形成した
金属薄膜を介してその電極と半導体装置側の半田バンプ
との間を仮接着し、その仮接着状態のまま加熱溶液中に
浸漬して半田バンプを溶融固着するようにしているので
、フラツクス残滓が半導体装置や配線基板の表面に付着
して装置の電気的特性や信頼性を損なうことがなく、ま
たフラックス洗浄の工程が不要で全体の工程が簡略にな
るという効果が得られる．In the second step, the semiconductor chip 11 is placed facing the wiring board 13, and the space between them is temporarily pressed. That is, the semiconductor chip 11 has its respective solder bumps 1
The semiconductor chip 11 is aligned on the wiring board 13 as shown in FIG. The aligned wiring board 13 is heated at a temperature of 160 to 170°C, which is slightly lower than the melting point of the solder.This causes some solid phase diffusion between the metal thin film 15 on the electrode 14 and the solder bump 12. occurs, and the metal thin film l
5, between the solder bumps 11 and the electrodes 14, that is, between the semiconductor chip 11 and the wiring board 13, as shown in FIG. 1 (3). In the fourth step, the semiconductor chip 11 is The temporarily bonded wiring board 13 is immersed for about 30 seconds in a bath of glycerin liquid at a temperature of about 250° C., which is higher than the melting point of the solder.This melts the solder bumps 12 and fixes them to the electrodes 14.After this, methanol The glycerin attached to the wiring board 13 is washed away in the solution, and the semiconductor chip 11 is finally mounted on the wiring board 13 as shown in FIG. 1 (4).
The figure is a process diagram showing a method for mounting a semiconductor device according to another embodiment of the present invention. In this mounting method, in the first step, the electrode 14 of the wiring board 13 is coated with a metal thin film 1 made of gold and having a thickness of 1000 mm.
5a is deposited and formed as shown in Figure 2 (1). In the next second step, the wiring board 13 is
The semiconductor chip 11 is positioned on top of the semiconductor chip 11 as shown in FIG. It is pressed against the wiring board 13. The pressing pressure is such that a force of about 2 to 3 g is applied to one solder bump 12. As a result, the metal thin film 15a on the electrode 14
Some solid phase diffusion occurs between the solder bump 11 and the electrode 14 through the metal thin film 15a.
In other words, the space between the semiconductor chip 11 and the wiring board 13 is
It is temporarily glued as shown in Figure 3. In the fourth step,
The wiring board 13 to which the semiconductor chip 11 is temporarily attached is immersed for about 30 seconds in a bath of glycerin solution at a temperature of about 250° C., as in the previous embodiment. This makes the solder bump 12
melts and sticks to the electrode 14. Finally, by cleaning the wiring board 13 in a methanol solution, the wiring board 13 is cleaned.
The glycerin attached to 3 is removed, and the result is shown in Figure 2 (4).
As shown in the figure, a semiconductor chip 11 is mounted on a wiring board 13. As described above, according to the semiconductor device mounting method of the present invention,
Temporarily bond the electrodes to the solder bumps on the semiconductor device side via a metal thin film formed on the electrodes of the wiring board without using flux, and solder by immersing the temporarily bonded state in a heated solution. Since the bumps are melted and fixed, flux residue will not adhere to the surface of the semiconductor device or wiring board and impair the electrical characteristics and reliability of the device, and there is no need for a flux cleaning process, simplifying the entire process. This has the effect of simplifying.
第１図は本発明の一実施例である半導体装置の実装方法
を示す工程図、第２図は本発明の他の実施例である半導
体装置の実装方法を示す工程図、第３図は従来の半導体
装置の実装方法を示す工程図である。
１１・・・半導体チップ、１２・・・半田バンプ、１３
配線基板、１４・・・電極、１５．１５ａ・・・金属薄
膜FIG. 1 is a process diagram showing a semiconductor device mounting method according to an embodiment of the present invention, FIG. 2 is a process diagram showing a semiconductor device mounting method according to another embodiment of the present invention, and FIG. 3 is a conventional FIG. 3 is a process diagram showing a method for mounting a semiconductor device. 11... Semiconductor chip, 12... Solder bump, 13
Wiring board, 14... Electrode, 15.15a... Metal thin film
Claims (1)
形成された対応する電極に突き合わせ、半田バンプを加
熱溶融させることによって配線基板に対して半導体装置
を電気的に接続する半導体装置の実装方法において、 配線基板の各電極上に親半田金属膜を形成する工程と、 半導体装置を前記配線基板に対向させて配置し、半導体
装置の半田バンプを配線基板の対応する電極に突き合わ
せた状態で半田の融点よりも低い温度で加熱および加圧
することによって、前記金属膜を介して半田バンプと配
線基板の電極との間をフラックスを用いないで仮接着す
る工程と、互いに仮接着された状態の半導体装置および
配線基板を、半田の融点以上の温度の液体中に浸漬して
半田バンプを溶融固着させる工程とを含むことを特徴と
する半導体装置の実装方法。[Claims] The semiconductor device is electrically connected to the wiring board by aligning a solder bump formed on an electrode of a semiconductor device with a corresponding electrode formed on a wiring board and heating and melting the solder bump. A method for mounting a semiconductor device includes the steps of: forming a parent solder metal film on each electrode of a wiring board; arranging a semiconductor device to face the wiring board; and placing solder bumps of the semiconductor device on corresponding electrodes of the wiring board. A step of temporarily adhering the solder bump and the electrode of the wiring board via the metal film without using flux by heating and pressurizing the butts at a temperature lower than the melting point of the solder, and temporarily adhering them to each other. 1. A method for mounting a semiconductor device, comprising the step of immersing a semiconductor device and a wiring board in a solder state in a liquid having a temperature equal to or higher than the melting point of the solder to melt and fix the solder bumps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1401990A JPH03218645A (en) | 1990-01-24 | 1990-01-24 | Mounting of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1401990A JPH03218645A (en) | 1990-01-24 | 1990-01-24 | Mounting of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03218645A true JPH03218645A (en) | 1991-09-26 |
Family
ID=11849485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1401990A Pending JPH03218645A (en) | 1990-01-24 | 1990-01-24 | Mounting of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03218645A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07176567A (en) * | 1993-12-16 | 1995-07-14 | Nec Corp | Manufacture of semiconductor device |
| JPH07226416A (en) * | 1994-01-31 | 1995-08-22 | Internatl Business Mach Corp <Ibm> | Semiconductor chip package and its preparation |
| JPH08172114A (en) * | 1994-12-20 | 1996-07-02 | Nec Corp | Board connection method |
| WO1996024459A1 (en) * | 1995-02-10 | 1996-08-15 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method of re-melting the metal coating on a contact surface |
| WO1996030939A1 (en) * | 1995-03-31 | 1996-10-03 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Process for surface contacting electronic components |
| US6121062A (en) * | 1993-08-13 | 2000-09-19 | Fujitsu Limited | Process of fabricating semiconductor unit employing bumps to bond two components |
| JP2021110875A (en) * | 2020-01-14 | 2021-08-02 | 三星電子株式会社Samsung Electronics Co., Ltd. | Manufacturing method for display device, display device, and intermediate for manufacturing display device |
-
1990
- 1990-01-24 JP JP1401990A patent/JPH03218645A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6121062A (en) * | 1993-08-13 | 2000-09-19 | Fujitsu Limited | Process of fabricating semiconductor unit employing bumps to bond two components |
| JPH07176567A (en) * | 1993-12-16 | 1995-07-14 | Nec Corp | Manufacture of semiconductor device |
| JPH07226416A (en) * | 1994-01-31 | 1995-08-22 | Internatl Business Mach Corp <Ibm> | Semiconductor chip package and its preparation |
| JPH08172114A (en) * | 1994-12-20 | 1996-07-02 | Nec Corp | Board connection method |
| WO1996024459A1 (en) * | 1995-02-10 | 1996-08-15 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method of re-melting the metal coating on a contact surface |
| US5845838A (en) * | 1995-02-10 | 1998-12-08 | Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. | Process for remelting a contact surface metallization |
| WO1996030939A1 (en) * | 1995-03-31 | 1996-10-03 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Process for surface contacting electronic components |
| US5785234A (en) * | 1995-03-31 | 1998-07-28 | Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. | Method of surface-contacting electronic components |
| JP2021110875A (en) * | 2020-01-14 | 2021-08-02 | 三星電子株式会社Samsung Electronics Co., Ltd. | Manufacturing method for display device, display device, and intermediate for manufacturing display device |
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