JPH07176567A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH07176567A JPH07176567A JP34349593A JP34349593A JPH07176567A JP H07176567 A JPH07176567 A JP H07176567A JP 34349593 A JP34349593 A JP 34349593A JP 34349593 A JP34349593 A JP 34349593A JP H07176567 A JPH07176567 A JP H07176567A
- Authority
- JP
- Japan
- Prior art keywords
- connection
- chip
- semiconductor chip
- temperature
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特にバンプを有する半導体装置の製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having bumps.
【０００２】[0002]
【従来の技術】従来、半導体装置の製造におけるフリッ
プチップ接続方法は、半田バンプをフラックスの粘着に
より仮接続し、その後溶融接続する方法と、導電性樹脂
を使用した接続方法が一般に実施されている。前者の方
法は、図５に示すように、フラックス（５）の粘着によ
り、半導体チップ（１）の半田バンプ（２）と回路基板
（４）のパッドメタル（３）を仮接続した後、溶融接続
を実施している。その後、電気的検査を実施し、不良半
導体チップに対して、半田バンプを加熱溶融して、不良
半導体チップを取り外し、リペアを実施している。2. Description of the Related Art Conventionally, as a flip chip connection method in the manufacture of a semiconductor device, a method of temporarily connecting solder bumps by adhesion of flux and then a melt connection, and a connection method using a conductive resin are generally implemented. . In the former method, as shown in FIG. 5, the solder bumps (2) of the semiconductor chip (1) and the pad metal (3) of the circuit board (4) are temporarily connected by adhesion of the flux (5) and then melted. Making a connection. After that, an electrical inspection is performed, the solder bumps are heated and melted on the defective semiconductor chip, the defective semiconductor chip is removed, and repair is performed.
【０００３】又、後者の接続方法については、例えば、
特開昭６３−３０８９２５号に提案されており、図６に
示すように基板（１）の配線パターン（２）上に導電性
低融点樹脂フィルム（３）を置き、レーザ（５）等によ
り、バンプを形成する部分を加熱し、フィルムを溶融さ
せ転写又は機械的圧力によりバンプを形成している。そ
して、バンプ形成部分に接着剤（６）を塗布し、バンプ
と半導体チップ（７）の接続端子とを位置合わせして、
１２０〜１５０℃加熱、５kg／cm2 で加圧して、樹脂を
溶融させ、導電粒子のみを接続部に残し、その後紫外線
を１５秒間照射して硬化させている。そして接続した半
導体チップの不良半導体チップに対して、４００℃で加
熱し、取り外した後、良品チップを供給している。Regarding the latter connection method, for example,
As disclosed in Japanese Patent Laid-Open No. 63-308925, as shown in FIG. 6, a conductive low melting point resin film (3) is placed on a wiring pattern (2) of a substrate (1) and a laser (5) is used. The bump forming portion is heated to melt the film and transfer or mechanical pressure forms the bump. Then, an adhesive (6) is applied to the bump formation portion, the bump and the connection terminal of the semiconductor chip (7) are aligned,
The resin is melted by heating at 120 to 150 ° C. and pressure of 5 kg / cm 2 , leaving only the conductive particles in the connection portion, and then irradiating with ultraviolet rays for 15 seconds to cure. Then, the defective semiconductor chip of the connected semiconductor chip is heated at 400 ° C. and removed, and then a non-defective chip is supplied.
【０００４】[0004]
【発明が解決しようとする課題】このような従来のフリ
ップチップ接続方法において、フラックスの粘着で仮接
続した半田バンプの接続では、粘着だけによる仮接続な
ので、半田バンプの高さばらつき、フラックスの塗布膜
の厚さばらつきが要因で、半田バンプと基板パットメタ
ルが接触しない箇所が発生する。そのため、溶融接続後
に接続オープン不良を起こしやすい。又、仮接続強度が
小さいため位置ずれが発生してしまう。更に、複数のチ
ップを１つの回路基板に搭載した場合、不良半導体チッ
プのリペアをする際に、半田バンプ材料を溶融して不良
半導体チップを取り外すことになるので、良品チップに
余計な熱ストレスが加わり、接続信頼性を劣化させると
いう問題があった。又導電性樹脂を使用した接続の場合
においても、リペア温度が４００℃と高いため、熱スト
レスが加わり、接続信頼性を劣化させるという問題点が
あった。更にリペア時に接着剤を除去しなければならな
いため、リペアプロセスが複雑であった。又、導電性樹
脂を使用した接続は、金属間接続に比べ、接続抵抗が不
安定で高いため、高速化を目的とした半導体チップには
不向きであるという欠点があった。In the conventional flip-chip connection method as described above, the solder bumps temporarily connected by the adhesive of the flux are connected only by the adhesive, so that the height variation of the solder bumps and the application of the flux are applied. Due to the variation in film thickness, there are places where the solder bumps do not contact the substrate pad metal. Therefore, a connection open failure is likely to occur after the fusion connection. Further, since the temporary connection strength is low, the position shift occurs. Further, when a plurality of chips are mounted on one circuit board, when repairing a defective semiconductor chip, the solder bump material is melted and the defective semiconductor chip is removed, so that a good chip is subjected to extra thermal stress. In addition, there is a problem that the connection reliability is deteriorated. Even in the case of connection using a conductive resin, since the repair temperature is as high as 400 ° C., there is a problem that thermal stress is applied and the connection reliability is deteriorated. Furthermore, the repair process was complicated because the adhesive had to be removed during repair. Further, the connection using the conductive resin has a drawback that the connection resistance is unstable and high as compared with the metal-to-metal connection, so that it is not suitable for a semiconductor chip for the purpose of speeding up.
【０００５】[0005]
【課題を解決するための手段】本発明は、上記課題を解
決するため、金属バンプを有する半導体チップを回路基
板上に実装しフリップチップ接続する半導体装置の製造
方法において、位置合わせされた前記半導体チップと回
路基板のパッドメタルを加熱温度、加圧力、加圧時間を
調節することにより、金属バンプ高さをレベリングし、
金属間拡散接続する仮接続工程を含むフリップチップ接
続を行うことを特徴とする半導体装置の製造方法であ
り、また、前記仮接続された半導体チップと回路基板を
溶融接続する工程を含むフリップチップ接続を行うこと
を特徴とする半導体装置の製造方法である。In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor device in which a semiconductor chip having metal bumps is mounted on a circuit board and flip-chip bonded to each other. By adjusting the heating temperature, pressure, and pressurization time of the chip and the pad metal of the circuit board, the metal bump height is leveled,
A method of manufacturing a semiconductor device, comprising a flip-chip connection including a temporary connection step of diffusion diffusion connection between metals, and a flip-chip connection including a step of melt-connecting the temporarily connected semiconductor chip and a circuit board. Is a method of manufacturing a semiconductor device.
【０００６】[0006]
【作用】本発明においては、フリップチップ接続方法と
して金属バンプ付き半導体チップと回路基板のパッドメ
タルとを、仮接続する際に、加熱・加圧力・加圧時間を
調節することにより、バンプ材料を変形させ、すべての
バンプと回路基板のパッドメタルを接触させ金属間拡散
接続を実施するもので、次のような作用をするものであ
る。 １．金属間拡散仮接続を実施しているので、仮接続実施
後、位置ずれすることなく容易に電気的検査が可能とな
る。 ２．仮接続時に、バンプの高さがレベリングされ、加圧
時間を調節することにより確実に、すべてのバンプとパ
ッドメタルが接触、接続できるため、溶融接続後に接続
オープン不良が発生しない。 ３．不良半導体チップのリペアが金属バンプの融点より
低い仮接続温度で容易に実施できるので、複数のチップ
を搭載した場合においても良品チップに対して、低熱ス
トレスで、接続信頼性が向上する。In the present invention, when the semiconductor chip with metal bumps and the pad metal of the circuit board are temporarily connected to each other by the flip chip connection method, the bump material is adjusted by adjusting the heating / pressurizing / pressurizing time. It is deformed to bring all the bumps into contact with the pad metal of the circuit board to carry out inter-metal diffusion connection, which has the following operation. 1. Since the inter-diffusion temporary connection is performed, the electrical inspection can be easily performed without displacement after the temporary connection is performed. 2. At the time of temporary connection, the bump height is leveled, and by adjusting the pressurizing time, all the bumps and the pad metal can be surely brought into contact with each other and connected, so that no connection open failure occurs after the melt connection. 3. Since the repair of the defective semiconductor chip can be easily carried out at a temporary connection temperature lower than the melting point of the metal bump, even when a plurality of chips are mounted, the connection reliability is improved with respect to a non-defective chip with low thermal stress.
【０００７】[0007]
【実施例】本発明の実施例を添付図面を参照しながら説
明する。図１は、本発明のフリップチップ接続フローチ
ャート及び接続断面図である。半田バンプ（２）付き半
導体チップ（１）と、パッドメタル（３）を形成した回
路基板（４）を搭載機（５）を使用して、位置合わせを
実施後（半田バンプ（２）の融点より低い温度で）加熱
・加圧力・加圧時間を調節して、半田バンプ（２）とパ
ッドメタル（３）とを金属間拡散による仮接続を実施す
る。半田は、加熱すると、小さな加圧力で容易に変形す
るので、すべての半田バンプ（２）がレベリングされ、
回路基板のパッドメタル（３）と確実に接触する。Embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a flip-chip connection flowchart and connection cross-sectional view of the present invention. The semiconductor chip (1) with the solder bumps (2) and the circuit board (4) on which the pad metal (3) is formed are aligned using the mounting machine (5) (melting point of the solder bumps (2)). By adjusting the heating / pressurizing / pressurizing time (at a lower temperature), the solder bump (2) and the pad metal (3) are temporarily connected by intermetallic diffusion. When the solder is heated, it deforms easily with a small pressure, so all the solder bumps (2) are leveled,
Make sure contact with the pad metal (3) of the circuit board.
【０００８】更に加圧時間を調節し、半田バンプ（２）
とパッドメタル（３）を互いに、金属相互拡散させ、仮
接続を実施する。その結果、金属間拡散接続により、接
続抵抗が小さいため、電気的検査が可能となる。検査
後、不良半導体チップに対しては半田バンプ（２）の溶
融温度より低い温度の仮接続温度で、取り外し、リペア
を実施する。そしてその後半田バンプを溶融して、強固
な接続を得る。図１中のフラックス（６）は、半田バン
プ（２）の酸化物を除去するためのものである。Further adjusting the pressing time, the solder bump (2)
And the pad metal (3) are mutually interdiffused to perform temporary connection. As a result, the connection resistance is small due to the metal-to-metal diffusion connection, so that an electrical test can be performed. After the inspection, the defective semiconductor chip is removed and repaired at a temporary connection temperature lower than the melting temperature of the solder bump (2). Then, after that, the solder bumps are melted to obtain a strong connection. The flux (6) in FIG. 1 is for removing the oxide of the solder bump (2).
【０００９】次に一例として、Ｐｂ−Ｓｎ合金（鉛−錫
合金）のＰｂ／Ｓｎ＝９５／５wt％（融点約３１４℃）
のバンプを形成した半導体チップと回路基板のパッドメ
タルを下層側からＮｉ（ニッケル）、Ａｕ（金）の構造
とした場合のフリップチップ接続を実施した結果につい
て説明する。Ｐｂ−Ｓｎ合金のＰｂ／Ｓｎ＝９５／５wt
％のバンプと回路基板の上層のパッドメタルＡｕとは、
約１５０℃以上で加熱、加圧すると、容易に相互拡散
し、Ｓｎ−Ａｕ，Ｐｂ−Ａｕの合金層を形成する。一般
にＳｎ−Ａｕ，Ｐｂ−Ａｕは、もろい合金層であるが、
初期的な電気的検査時には問題ない。又、仮接続条件と
しては、温度１５０℃〜２８０℃、加圧力１．０×１０
-4gf／μｍ2 〜５．０×１０-3gf／μｍ2 、加圧時間１
５秒以上が好ましい。この条件によれば、仮接続後及び
溶融接続後に、接続オープンやショートは発生しない。Next, as an example, Pb / Sn of a Pb-Sn alloy (lead-tin alloy) = 95/5 wt% (melting point: about 314 ° C)
The results of performing flip-chip connection in the case where the semiconductor chip on which the bumps are formed and the pad metal of the circuit board have a structure of Ni (nickel) and Au (gold) from the lower layer side will be described. Pb / Sn = 95/5 wt of Pb-Sn alloy
% Of the bumps and the pad metal Au on the upper layer of the circuit board,
When heated and pressed at a temperature of about 150 ° C. or higher, they easily diffuse into each other to form an Sn—Au, Pb—Au alloy layer. In general, Sn-Au and Pb-Au are brittle alloy layers,
There is no problem at the initial electrical inspection. The temporary connection conditions are a temperature of 150 ° C. to 280 ° C. and a pressure of 1.0 × 10.
-4 gf / μm 2 to 5.0 × 10 −3 gf / μm 2 , pressurization time 1
5 seconds or more is preferable. According to this condition, no connection open or short circuit occurs after the temporary connection and the fusion connection.
【００１０】図２，及び図３は、Ｐｂ−Ｓｎ合金のＰｂ
／Ｓｎ＝９５／５wt％のバンプを使用した場合の仮接続
温度と、仮接続後の接続オープン、ショート発生率の関
係を示したもの、及び、Ｐｂ／Ｓｎ＝９５／５wt％のバ
ンプを使用した場合の仮接続温度と、溶融接続後の接続
オープン、ショート発生率の関係を示したものである。
図２，及び図３は、それぞれＰｂ／Ｓｎ＝９５／５wt％
のバンプ２００個を形成した半導体チップと回路基板の
パッドメタル構造を下層側からＮｉ，Ａｕとしたものと
のフリップチップ仮接続温度と仮接続後（図２）及び溶
融接続後（図３）の接続オープン、ショート発生率を示
したものである。仮接続温度を、１５０℃〜２８０℃で
実施したものでは、仮接続後、溶融接続後とも、接続オ
ープン、ショートは発生していない。又、逆に、従来技
術のように、常温〜１００℃で、電気的に接続されてい
ない仮接続では、溶融接続後に、接続オープン不良を発
生し易い結果が得られている。2 and 3 show the Pb of Pb-Sn alloy.
/ Sn = 95 / 5wt% bumps used, showing the relation between temporary connection temperature and connection open / short circuit occurrence rate after temporary connection, and Pb / Sn = 95 / 5wt% bumps used In this case, the relationship between the temporary connection temperature and the connection open / short circuit occurrence rate after fusion connection is shown.
2 and 3 show Pb / Sn = 95/5 wt%, respectively.
Of the semiconductor chip on which 200 bumps are formed and the pad metal structure of the circuit board made of Ni and Au from the lower layer side after the flip chip temporary connection temperature and after the temporary connection (FIG. 2) and after the melt connection (FIG. 3). It shows the rate of occurrence of open connections and short circuits. In the case where the temporary connection temperature is 150 ° C. to 280 ° C., no connection open or short circuit occurs even after the temporary connection and the fusion connection. On the contrary, as in the prior art, at the room temperature to 100 ° C., the temporary connection which is not electrically connected has the result that the connection open failure is likely to occur after the fusion connection.
【００１１】図４には、Ｐｂ−Ｓｎ合金のＰｂ／Ｓｎ＝
９５／５wt％のバンプの熱圧縮変形特性の実験データを
示したものである。図中の（１）（２）（３）は、それ
ぞれ（１）Ｐｂ／Ｓｎ＝９５／５wt％のバンプに約１．
２×１０-5gf／μｍ2 で加圧したもの、（２）約１．２
×１０-4gf／μｍ2 で加圧したもの、（３）約６．０×
１０-4gf／μｍ2 で加圧した時のＰｂ／Ｓｎ＝９５／５
wt％バンプの熱圧縮変形率を示している。ここで、熱圧
縮変形率とは、加圧で変形後のバンプ高さをもとのバン
プ高さで割ったものを％で表示したものである。１５０
℃以上で加圧力差の影響が現れることから、Ｐｂ／Ｓｎ
＝９５／５wt％半田は、軟化していることがわかる。お
およそ１．２×１０-4gf／μｍ2 の加圧力で２５０℃で
は、全体の約５％圧縮変形される。図４の実験データか
ら仮接続温度が１５０℃〜２８０℃で：加圧力が１．０
×１０-4gf／μｍ2 〜５．０×１０-3gf／μｍ2 では、
Ｐｂ／Ｓｎ＝９５／５wt％半田バンプは容易に変形し
て、バンプ高さがレベリングされることがわかる。In FIG. 4, Pb / Sn of Pb-Sn alloy =
It shows experimental data of thermal compression deformation characteristics of 95/5 wt% bumps. In the figure, (1), (2), and (3) are about 1% for the bumps of (1) Pb / Sn = 95/5 wt%, respectively.
Pressurized with 2 × 10 -5 gf / μm 2 , (2) about 1.2
× 10 −4 gf / μm 2 pressurized, (3) about 6.0 ×
Pb / Sn = 95/5 when pressurized at 10 −4 gf / μm 2
The wt% bump thermal deformation ratio is shown. Here, the thermal compression deformation rate is a value obtained by dividing the bump height after deformation by pressure by the original bump height and expressing it in%. 150
Since the effect of the pressure difference appears above ℃, Pb / Sn
= 95/5 wt% solder is softened. At 250 ° C. under a pressure of approximately 1.2 × 10 −4 gf / μm 2 , approximately 5% of the total compression deformation occurs. From the experimental data of FIG. 4, when the temporary connection temperature is 150 ° C. to 280 ° C .: the pressing force is 1.0
At × 10 -4 gf / μm 2 to 5.0 × 10 -3 gf / μm 2 ,
It can be seen that the Pb / Sn = 95/5 wt% solder bump is easily deformed and the bump height is leveled.
【００１２】Ｐｂ／Ｓｎ＝９５／５wt％バンプと回路基
板のパッドメタルとの間のＰｂ−Ａｕ，Ｓｎ−Ａｕの合
金層の溶融温度は、仮接続温度と同等になるので、低温
（１５０℃〜２８０℃）で取り外しが可能となる。リペ
ア回数は、それぞれ仮接続温度を１５０℃にした場合、
１０回、２００℃にした場合６回、２８０℃にした場合
３回程度である。上記実施例は、主にＰｂ−Ｓｎ合金の
Ｐｂ／Ｓｎ＝９５／５wt％の半田について説明したが、
本発明のフリップチップ接続方法は本発明の主旨にかな
うものであれば金属材料であればよく、金属バンプとし
ては例えば半田バンプが用いられ、具体的には、Ｐｂ−
Ｓｎ合金の組成がＰｂ／Ｓｎ＝３７／６３wt％、Ａｕ−
Ｓｎ合金では、その組成がＡｕ／Ｓｎ＝８０／２０wt％
等の金属材料にも同様に実施できる。また、バンプの形
成方法、形状等が異なるものにでも同様に実施できる。Since the melting temperature of the alloy layer of Pb-Au and Sn-Au between the Pb / Sn = 95/5 wt% bump and the pad metal of the circuit board is equal to the temporary connection temperature, it is low (150 ° C.). It can be removed at ~ 280 ° C). When the temporary connection temperature is 150 ℃,
10 times, 6 times at 200 ° C. and 3 times at 280 ° C. Although the above-mentioned embodiments mainly describe the solder of Pb / Sn = 95/5 wt% of the Pb-Sn alloy,
The flip-chip connection method of the present invention may be made of a metal material as long as it is in accordance with the gist of the present invention. As the metal bump, for example, a solder bump is used.
The composition of Sn alloy is Pb / Sn = 37/63 wt%, Au-
The composition of Sn alloy is Au / Sn = 80 / 20wt%
The same can be applied to metal materials such as. Further, the bumps can be formed in the same manner even if they have different bump forming methods and shapes.
【００１３】[0013]
【発明の効果】上述のように本発明によれば、フリップ
チップ接続方法が、仮接続を、加熱・加圧力・加圧時間
を調節することによって、バンプを変形させ、すべての
バンプと回路基板のパッドメタルと接触させ、バンプ材
料の融点より低い温度で、金属間拡散接続を実施するよ
うにしたので、 １．仮接続後、位置ずれすることなく容易に電気的検査
が可能となる。 ２．バンプ高さがレベリングされるので、溶融接続後に
接続オープン不良が発生しない。 ３．不良半導体チップのリペアが、仮接続後に実施可能
となり、金属バンプの融点より低い仮接続温度で、容易
に実施できる。これにより、複数のチップを搭載した場
合においても、良品チップに対して、低熱ストレスでリ
ペアが実施できる。 等これらの利点により、フリップチップ接続信頼性が向
上するという効果を奏するものである。As described above, according to the present invention, the flip chip bonding method deforms the bumps by adjusting the heating / pressurizing / pressurizing time in the temporary bonding, and all the bumps and the circuit board. Since the intermetallic diffusion connection is carried out at a temperature lower than the melting point of the bump material by contacting the pad metal of 1. After the temporary connection, electrical inspection can be easily performed without displacement. 2. Since the bump height is leveled, a connection open defect does not occur after fusion connection. 3. The repair of the defective semiconductor chip can be performed after the temporary connection, and can be easily performed at the temporary connection temperature lower than the melting point of the metal bump. As a result, even when a plurality of chips are mounted, the good chips can be repaired with low thermal stress. Due to these advantages, the flip chip connection reliability is improved.
【図１】本発明の実施例であるフリップチップ接続フロ
ーチャート及び接続断面図。FIG. 1 is a flip-chip connection flowchart and connection cross-sectional view that are an embodiment of the present invention.
【図２】Ｐｂ−Ｓｎ合金のバンプを使用した場合の仮接
続温度と、仮接続後の接続オープン、ショート発生率の
関係を示した図。FIG. 2 is a diagram showing a relationship between a temporary connection temperature when a Pb-Sn alloy bump is used and a connection open / short circuit occurrence rate after the temporary connection.
【図３】Ｐｂ−Ｓｎ合金のバンプを使用した場合の仮接
続温度と、溶融接続後の接続オープン、ショート発生率
の関係を示した図。FIG. 3 is a diagram showing a relationship between a temporary connection temperature when a bump of Pb-Sn alloy is used and a connection open / short circuit occurrence rate after fusion connection.
【図４】Ｐｂ−Ｓｎ合金のバンプの熱圧縮変形率を示し
た図。FIG. 4 is a diagram showing a thermal compression deformation rate of a Pb-Sn alloy bump.
【図５】従来のフリップチップ接続フローチャート及び
接続断面図。FIG. 5 is a conventional flip-chip connection flowchart and connection cross-sectional view.
【図６】従来のフリップチップ接続フローチャート及び
接続断面図。FIG. 6 is a conventional flip-chip connection flowchart and connection cross-sectional view.
１ 半導体チップ ２ 半田バンプ ３ パッドメタル ４ 回路基板 ５ 搭載機 ６ フラックス 1 semiconductor chip 2 solder bumps 3 pad metal 4 circuit board 5 mounting machine 6 flux
───────────────────────────────────────────────────── フロントページの続き (72)発明者 日下 輝雄 東京都港区芝五丁目７番１号 日本電気株 式会社内 ─────────────────────────────────────────────────── --Continued front page (72) Inventor Teruo Kusaka 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation
Claims (4)
基板上に実装しフリップチップ接続する半導体装置の製
造方法において、位置合わせされた前記半導体チップと
回路基板のパッドメタルを加熱温度、加圧力、加圧時間
を調節することにより、金属バンプ高さをレベリング
し、金属間拡散接続する仮接続工程を含むフリップチッ
プ接続を行うことを特徴とする半導体装置の製造方法。1. In a method of manufacturing a semiconductor device in which a semiconductor chip having metal bumps is mounted on a circuit board and flip-chip connected, the aligned semiconductor chip and the pad metal of the circuit board are heated at a temperature, a pressure applied, and a pressure applied. A method of manufacturing a semiconductor device, which comprises performing a flip chip connection including a temporary connection step of leveling the metal bump by adjusting the pressure time and performing diffusion connection between metals.
ップと回路基板を溶融接続する工程を含むフリップチッ
プ接続を行うことを特徴とする半導体装置の製造方法。2. A method of manufacturing a semiconductor device, which comprises performing a flip chip connection including a step of fusion-bonding the temporarily connected semiconductor chip according to claim 1 and a circuit board.
間拡散による仮接続後に電気的検査を実施することを特
徴とする請求項１または２に記載の半導体装置の製造方
法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip and the circuit board are electrically inspected after temporary connection by metal diffusion.
に対して、金属バンプの融点より低い温度でリペアを実
施することを特徴とする請求項１乃至３のいずれかに記
載の半導体装置の製造方法。4. The semiconductor device according to claim 1, wherein after the electrical inspection, the defective semiconductor chip is repaired at a temperature lower than the melting point of the metal bump. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5343495A JP3014020B2 (en) | 1993-12-16 | 1993-12-16 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5343495A JP3014020B2 (en) | 1993-12-16 | 1993-12-16 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07176567A true JPH07176567A (en) | 1995-07-14 |
| JP3014020B2 JP3014020B2 (en) | 2000-02-28 |
Family
ID=18361962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5343495A Expired - Fee Related JP3014020B2 (en) | 1993-12-16 | 1993-12-16 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3014020B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6121576A (en) * | 1998-09-02 | 2000-09-19 | Micron Technology, Inc. | Method and process of contact to a heat softened solder ball array |
| US6994243B2 (en) * | 1997-03-13 | 2006-02-07 | International Business Machines Corporation | Low temperature solder chip attach structure and process to produce a high temperature interconnection |
| JP2015053434A (en) * | 2013-09-09 | 2015-03-19 | 富士通株式会社 | Manufacturing method of semiconductor device |
| CN111755347A (en) * | 2019-03-28 | 2020-10-09 | 美科米尚技术有限公司 | Method for limiting micro-device on conductive pad |
| CN114535148A (en) * | 2022-01-17 | 2022-05-27 | 广东气派科技有限公司 | Pressure measuring device suitable for gravity separator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0319251A (en) * | 1989-06-15 | 1991-01-28 | Matsushita Electric Ind Co Ltd | Inspection method for semiconductor device |
| JPH03218645A (en) * | 1990-01-24 | 1991-09-26 | Sharp Corp | Mounting of semiconductor device |
| JPH0499039A (en) * | 1990-08-06 | 1992-03-31 | Fujitsu Ltd | Connection of tab tape |
-
1993
- 1993-12-16 JP JP5343495A patent/JP3014020B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0319251A (en) * | 1989-06-15 | 1991-01-28 | Matsushita Electric Ind Co Ltd | Inspection method for semiconductor device |
| JPH03218645A (en) * | 1990-01-24 | 1991-09-26 | Sharp Corp | Mounting of semiconductor device |
| JPH0499039A (en) * | 1990-08-06 | 1992-03-31 | Fujitsu Ltd | Connection of tab tape |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6994243B2 (en) * | 1997-03-13 | 2006-02-07 | International Business Machines Corporation | Low temperature solder chip attach structure and process to produce a high temperature interconnection |
| US6121576A (en) * | 1998-09-02 | 2000-09-19 | Micron Technology, Inc. | Method and process of contact to a heat softened solder ball array |
| US6329637B1 (en) | 1998-09-02 | 2001-12-11 | Micron Technology, Inc. | Method and process of contract to a heat softened solder ball array |
| US6420681B1 (en) | 1998-09-02 | 2002-07-16 | Micron Technology, Inc. | Method and process of contact to a heat softened solder ball array |
| US6614003B2 (en) | 1998-09-02 | 2003-09-02 | Micron Technology, Inc. | Method and process of contact to a heat softened solder ball array |
| US6967307B2 (en) | 1998-09-02 | 2005-11-22 | Micron Technology, Inc. | Method and process of contact to a heat softened solder ball array |
| JP2015053434A (en) * | 2013-09-09 | 2015-03-19 | 富士通株式会社 | Manufacturing method of semiconductor device |
| CN111755347A (en) * | 2019-03-28 | 2020-10-09 | 美科米尚技术有限公司 | Method for limiting micro-device on conductive pad |
| CN114535148A (en) * | 2022-01-17 | 2022-05-27 | 广东气派科技有限公司 | Pressure measuring device suitable for gravity separator |
| CN114535148B (en) * | 2022-01-17 | 2024-02-09 | 广东气派科技有限公司 | Pressure measurement device suitable for gravity type separator |
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| Publication number | Publication date |
|---|---|
| JP3014020B2 (en) | 2000-02-28 |
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