JPH01309336A - Semiconductor container - Google Patents

Semiconductor container

Info

Publication number
JPH01309336A
JPH01309336A JP63140847A JP14084788A JPH01309336A JP H01309336 A JPH01309336 A JP H01309336A JP 63140847 A JP63140847 A JP 63140847A JP 14084788 A JP14084788 A JP 14084788A JP H01309336 A JPH01309336 A JP H01309336A
Authority
JP
Japan
Prior art keywords
chip
filler material
brazing filler
semiconductor container
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63140847A
Other languages
Japanese (ja)
Inventor
Shuji Kanamori
金森　修二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63140847A priority Critical patent/JPH01309336A/en
Publication of JPH01309336A publication Critical patent/JPH01309336A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent the adhesion of brazing filler material to the surface of a chip in mounting, in a semiconductor container in which a plurality of the chips are mounted, by forming a groove which surrounds the peripheral part of each chip. CONSTITUTION:A groove 4 is formed at a peripheral part which surrounds a region where each chip 3 is mounted in a semiconductor container 1. A mounting brazing filler material 2 is heated and fused on the container 1. Thereafter, the chip 3 is attached to the specified position. Pressure is applied on the chip 3 so that bobbles are not formed between the chip 3 and the brazing filler material 2. The chip is moved in the lateral direction and bonded, thereby the conformability is improved. The surplus brazing filler material 2 is pushed into the groove 4 around the chip 3. In this way, the adhesion of the brazing filler material 2 to the surface of the chip in mounting is prevented.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体容器に関し、特に、複数のチップを有
する超高周波大電力用トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor container, and more particularly to an ultra-high frequency, high power transistor having a plurality of chips.

従来の技術 従来、この種の超高周波大電力用トランジスタは、浅い
接合が動作時の発熱による接合破壊を防止するために１
個々の出力を小さくし、複数のチップを並列に接続した
りチップを薄くしてコレクタ低抗を小さくして出力を補
う方法を行っていた。Conventional technology Conventionally, this type of ultra-high frequency, high power transistor has a shallow junction that has a shallow junction to prevent junction breakdown due to heat generation during operation.
The methods used were to reduce the individual output, connect multiple chips in parallel, or make the chips thinner to reduce the collector resistance to compensate for the output.

この種のチップは第４図（ａ）、（ｂ）の様に鑞材によ
り半導体容器にマウントする技術が知られている。A known technique is to mount this type of chip in a semiconductor container using a soldering material as shown in FIGS. 4(a) and 4(b).

発明が解決しようとする課題 −」二連した従来のマウント方法は、複数のチップを接
着するために多量の鑞材を使用するので、チップを薄く
すると表面に余分な鑞材が廻り込むという欠点がある。Problems to be Solved by the Invention - "The conventional dual mounting method uses a large amount of solder material to bond multiple chips, so when the chips are made thinner, the excess solder material wraps around the surface, which is a drawback. There is.

本発明は従来の上記実情に鑑みてなされたものであり、
従って本発明の目的は、従来の技術に内在するーｌ―記
欠点を解消し、マウント時に鑞材がチップ表面に付着す
ることを防止することを１＋Ｊ能とした新規な半導体容
器を提供することにある。The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel semiconductor container which eliminates the drawbacks inherent in the prior art and has the ability to prevent solder material from adhering to the surface of a chip during mounting. It is in.

発明の従来技術に対する相違点 上述した従来のマウント構造に対し、本発明は、チップ
周辺の容器に溝を有しているという相違点がある。Differences between the present invention and the prior art The present invention differs from the conventional mount structure described above in that the container around the chip has a groove.

課題を解決するための手段 前記目的を達成する為に１本発明に係る半導体容器は、
マウント時の余分な鑞材をチップ周辺の１ｂ￥に分離す
る構造を有している。Means for Solving the Problems In order to achieve the above object, a semiconductor container according to the present invention includes:
It has a structure in which excess solder material during mounting is separated into 1b around the chip.

実施例 次に本発明をその好ましい一実施例について図面を参照
して具体的に説明する。Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

第１図（ａ）および（ｂ）は本発明による第１の実施例
を示す正面図および（ａ）のｘ−ｘ’線に沿って切断し
矢印の方向に見た縦断面図である。FIGS. 1(a) and 1(b) are a front view showing a first embodiment of the present invention, and a longitudinal cross-sectional view taken along line xx' in FIG. 1(a) and viewed in the direction of the arrow.

第１図（ａ）、（ｂ）を参照するに、半導体容器りのチ
ップ３をマウントする領域を取囲む周辺部には溝４が形
成されている。Referring to FIGS. 1(a) and 1(b), a groove 4 is formed in the peripheral portion surrounding the area in which the chip 3 of the semiconductor container is mounted.

半導体容器上上にマウント鑞材２を４００〜５００°Ｃ
に加熱して溶かした後にチップ３を所定の位置に付着さ
せる。このとき、チップ３とマウント鑞材２間に気泡が
出来ない様にチップ３上から圧力をかけて、横方向に移
動させながら接着させるとよくなじむ様になり、余分な
鑞材はチップ３周辺の溝４に押し流されてしまうことに
なる。Mount the solder material 2 on top of the semiconductor container at 400-500°C.
After heating and melting it, the chip 3 is attached to a predetermined position. At this time, to prevent air bubbles from forming between the chip 3 and the mount solder material 2, apply pressure from above the chip 3 and move it laterally while adhering it. This means that they will be swept away by the groove 4.

この作業は複数のチップを同時に接着するのではなく個
々に独立して行われる。これにより、チップ厚さを十分
薄くすることが可能になる。例えば、従来５００μｍ前
後の厚さを１００μｍ程度にすればコレクタ抵抗は厚さ
分だけ減少するので、約１１５にすることができる。This work is done individually, rather than by gluing multiple chips together. This makes it possible to make the chip thickness sufficiently thin. For example, if the conventional thickness is about 500 μm, if it is reduced to about 100 μm, the collector resistance will be reduced by the thickness, so it can be reduced to about 115 μm.

第２図および第３図は本発明による第２、第３の実施例
を示す縦断面図である。FIGS. 2 and 3 are longitudinal sectional views showing second and third embodiments of the present invention.

第２図、第３図を参照するに、この第２、第３の実施例
では、余分なマウント鑞材を溝に入り易くするために、
チップ周辺に段部１ａ（第２図）およびテーパ部Ｌｂ（
第３図）が設けられている。Referring to FIGS. 2 and 3, in the second and third embodiments, in order to make it easier for the excess mounting solder material to enter the groove,
A stepped portion 1a (Fig. 2) and a tapered portion Lb (
(Fig. 3) is provided.

発明の詳細 な説明した様に、本発明によれば、余分なマウント鑞材
がチップ周辺の溝に吸収することを利用して、マウント
時にチップ表面に鑞材が付着することを防止できる効果
が得られる。As described in detail, the present invention has the effect of preventing the adhesion of solder material to the chip surface during mounting by utilizing the fact that excess mounting solder material is absorbed into the groove around the chip. can get.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）、（ｂ）は本発明に係る半導体容器の正面
図＜ａ）、（ａ）の×−Ｘ′線に沿った縦断面図（ｂ）
。 第２図および第３図は本発明に係る半導体容器の第２、
第３の実施例を示す縦断面図、第４図（ａ）、（ｂ）は
従来の容器の正面図（ａ）、（ａ）のＹ−Ｙ’線に沿っ
た縦断面図（ｂ）である。 ■、１０．、、半導体容器、２．２０．、．７ウント鑞
材、３．３０．、、チップ、４００．溝 −Ｘ　　　　　　　　　　７　　　升 −」FIGS. 1(a) and 1(b) are a front view of a semiconductor container according to the present invention, and FIG. 1(b) is a longitudinal cross-sectional view taken along the line
. FIGS. 2 and 3 show a second semiconductor container according to the present invention,
A vertical cross-sectional view showing the third embodiment; FIGS. 4(a) and 4(b) are a front view of a conventional container; It is. ■, 10. ,, semiconductor container, 2.20. ,．． 7 und brazing material, 3.30. ,,chip,400. Groove-X 7 squares-”

Claims (1)

【特許請求の範囲】[Claims] 　複数のチップをマウントする半導体容器において、各
チップ周辺部を取り囲む溝を有することを特徴とする半
導体容器。A semiconductor container for mounting a plurality of chips, characterized in that the semiconductor container has a groove surrounding a peripheral portion of each chip.
JP63140847A 1988-06-08 1988-06-08 Semiconductor container Pending JPH01309336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63140847A JPH01309336A (en) 1988-06-08 1988-06-08 Semiconductor container

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63140847A JPH01309336A (en) 1988-06-08 1988-06-08 Semiconductor container

Publications (1)

Publication Number Publication Date
JPH01309336A true JPH01309336A (en) 1989-12-13

Family

ID=15278109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63140847A Pending JPH01309336A (en) 1988-06-08 1988-06-08 Semiconductor container

Country Status (1)

Country Link
JP (1) JPH01309336A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100660660B1 (en) * 2002-06-11 2006-12-21 후지 덴키 홀딩스 가부시키가이샤 Semiconductor device
JP2018029201A (en) * 2017-10-13 2018-02-22 ローム株式会社 Semiconductor device
JP2019062245A (en) * 2019-01-29 2019-04-18 ローム株式会社 Semiconductor device
US10777542B2 (en) 2014-03-04 2020-09-15 Rohm Co., Ltd. Power semiconductor module for an inverter circuit and method of manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100660660B1 (en) * 2002-06-11 2006-12-21 후지 덴키 홀딩스 가부시키가이샤 Semiconductor device
US10777542B2 (en) 2014-03-04 2020-09-15 Rohm Co., Ltd. Power semiconductor module for an inverter circuit and method of manufacturing the same
JP2018029201A (en) * 2017-10-13 2018-02-22 ローム株式会社 Semiconductor device
JP2019062245A (en) * 2019-01-29 2019-04-18 ローム株式会社 Semiconductor device

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