JPS58220434A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58220434A
JPS58220434A JP57104267A JP10426782A JPS58220434A JP S58220434 A JPS58220434 A JP S58220434A JP 57104267 A JP57104267 A JP 57104267A JP 10426782 A JP10426782 A JP 10426782A JP S58220434 A JPS58220434 A JP S58220434A
Authority
JP
Japan
Prior art keywords
bonding
die
wire
layer
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57104267A
Other languages
Japanese (ja)
Inventor
Minoru Hirai
平井　稔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57104267A priority Critical patent/JPS58220434A/en
Publication of JPS58220434A publication Critical patent/JPS58220434A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To facilitate the bonding of a wire to a die mounting part, by providing a semiconductor package with a region which hardly permits a bonding material to be wet in a die bonding operation but allows a wire bonding. CONSTITUTION:In a die mounting part 1, an Al layer 8 is provided outside bonding parts by evaporation or plating which prevents solder from wetting but permits a wire bonding. The layer 8 blocks the flowage of the molten solder, and it is made possible to bond a thin metal wire 9 to the layer 8 in the mounting part 1. Accordingly, the operation is facilitated.

Description

【発明の詳細な説明】 本発明は半導体装置に関し、半導体収納容器にダイボッ
ド時におけるダイボンド材が濡れにくく、かつ、ワイヤ
ーボンドの可能な領域を設け、ダイアタッチ部へのワイ
ヤーボンドを容易にするものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and a semiconductor storage container is provided with an area where die bonding material is difficult to get wet during die bonding and where wire bonding is possible, thereby facilitating wire bonding to a die attach portion. It is.

従来の半田ダイボンドについて第１図、第２図（ＩＬ）
、　（ｂ）に従って説明する。Figures 1 and 2 (IL) of conventional solder die bonding
, (b) will be explained.

第１図のごとく半導体収納容器のダイアタッチ部１に半
田２を敷き、その上に半導体素子３を置き加熱すること
で第２図（＆）、　（ｂ）の様に半田を溶解させて半導
体素子を接着する。ダイアタッチ部１には金属のメッキ
層４がある。As shown in Figure 1, solder 2 is spread on the die attach part 1 of the semiconductor storage container, and by placing the semiconductor element 3 on top of it and heating it, the solder is melted as shown in Figures 2 (&) and (b), and the semiconductor Glue the elements. The die attach portion 1 has a metal plating layer 4.

ダイボンド後、外部電極群５と半導体素子上の電極群６
とを金属線７で接続するが、一部の半導体素子では電極
群６の中の特定の電極とダイアタッチ部１とを接続する
ことがある。この時に、溶解して流れた半田がダイアタ
ッチ部１の全面に広がっていたのではダイアタッチ部に
超音波法、熱圧着法、超音波熱圧着法等によるワイヤー
ボンドはできない。仮に半田がダイアタッチ部１全面に
広がっていなかったとしても、半田が流れていない部分
は全くランダムであり、この部分へワイヤーボンドする
ことは容易ではない。After die bonding, the external electrode group 5 and the electrode group 6 on the semiconductor element
However, in some semiconductor devices, a specific electrode in the electrode group 6 and the die attach portion 1 may be connected. At this time, if the melted and flowing solder spreads over the entire surface of the die attach part 1, wire bonding cannot be performed on the die attach part by an ultrasonic method, a thermocompression bonding method, an ultrasonic thermocompression bonding method, or the like. Even if the solder does not spread over the entire surface of the die attach portion 1, the portions where the solder does not flow are completely random, and it is not easy to wire bond to these portions.

そこで本発明は上記欠点を除去するために、ダイアタッ
チ部１に半田が流れに＜＜、かつ、超音波法、熱圧着法
、超音波熱圧着法等によるワイヤーボンドが可能な領域
を設けることで、ダイアタッチ部へのワイヤーボンドを
容易にするものである。Therefore, in order to eliminate the above-mentioned drawbacks, the present invention provides an area in the die attach part 1 where solder can flow and where wire bonding can be performed by ultrasonic method, thermocompression bonding method, ultrasonic thermocompression bonding method, etc. This facilitates wire bonding to the die attach area.

第３図（＆）、　（ｂ）は本発明の一実施例にかかる半
導体装置を示すものである。第２図と同一部分には同一
番号を付している。ダイアタッチ部１の中で、かつ、半
導体素子が実際に接着される部分の外側の部分に、半田
が濡れず、かつ、超音波法、熱圧着法、超音波熱圧着法
等によるワイヤーボンドが可能な金属例えばムｌで蒸着
層又はメッキ層８を設ける。この層により溶解した半田
の流動は防げ、さらにダイアタッチ部１の蒸着層または
メッキ層８に金属細線９によるワイヤーボンドが可能に
なる。FIGS. 3(&) and 3(b) show a semiconductor device according to an embodiment of the present invention. The same parts as in FIG. 2 are given the same numbers. In the die attach part 1 and outside the part where the semiconductor element is actually bonded, the solder does not get wet and wire bonding by ultrasonic method, thermocompression bonding method, ultrasonic thermocompression bonding method, etc. is applied. A vapor deposited or plated layer 8 is provided with a possible metal, for example mulch. This layer prevents the melted solder from flowing, and also enables wire bonding to the vapor deposited layer or plating layer 8 of the die attach portion 1 using the thin metal wire 9.

以上のように、本発明では半導体収納容器のダイアタッ
チ部にダイポンド材が濡れにくり、かつ、ワイヤーボン
ドが可能り、領域を有するだめダイボンド材の不必要な
濡れを防げダイアタッチ部へのワイヤーボンドを容易に
行うことができる。As described above, in the present invention, it is possible to prevent the die bond material from getting wet in the die attach area of the semiconductor storage container, and also to enable wire bonding, and to prevent unnecessary wetting of the die bond material having the area. Bonding can be done easily.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は半田ダイポンドされた半導体素子の要部概略断
面図、第２図（ａ）、Φ）は従来の中空型半導体収納容
器の正面図、概略要部断面図、第３図（ａ）。 Φ）は本発明の一実施例にかかる半導体収納容器の正面
図！概略要部断面図である。 １・・・・・・ダイアタッチ部、３・・・・・・半導体
素子、４・・・・・・金属のメッキ層、６・・・・・・
外部電極群、８・・・・・・蒸着まだはメッキ層、９・
・・・・・金属細線。Fig. 1 is a schematic cross-sectional view of the main part of a solder die-bonded semiconductor element, Fig. 2 (a), Φ) is a front view and a schematic cross-sectional view of the main part of a conventional hollow semiconductor storage container, and Fig. 3 (a) . Φ) is a front view of a semiconductor storage container according to an embodiment of the present invention! FIG. 2 is a schematic cross-sectional view of essential parts. 1...Die attach portion, 3...Semiconductor element, 4...Metal plating layer, 6...
External electrode group, 8... vapor deposited plating layer, 9.
...Thin metal wire.

Claims (1)

【特許請求の範囲】[Claims] （１）半導体収納容器の半導体素子を接着する部分に、
半導体素子をダイボンドする時にダイボンド材が濡れに
＜＜、かつワイヤーボンドが可能な領域を有する半導体
装置。 し）領域が、半田が流れに＜＜、かつワイヤーボンドが
可能な金属の蒸着層又はメッキ層よりなることを特徴と
する特許請求範囲第１項に記載の半導体装置。(1) At the part of the semiconductor storage container where the semiconductor element is to be glued,
A semiconductor device having a region where a die-bonding material gets wet when die-bonding a semiconductor element and where wire bonding is possible. 2. The semiconductor device according to claim 1, wherein the region (b) is made of a vapor deposited layer or a plated layer of metal in which solder flows and wire bonding is possible.
JP57104267A 1982-06-16 1982-06-16 Semiconductor device Pending JPS58220434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57104267A JPS58220434A (en) 1982-06-16 1982-06-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57104267A JPS58220434A (en) 1982-06-16 1982-06-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58220434A true JPS58220434A (en) 1983-12-22

Family

ID=14376148

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57104267A Pending JPS58220434A (en) 1982-06-16 1982-06-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58220434A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903114A (en) * 1985-10-01 1990-02-20 Fujitsu Limited Resin-molded semiconductor
US6251469B1 (en) 1997-03-19 2001-06-26 International Business Machines, Corporation Method of rendering a substrate selectively non-wettable chip carrier with enhanced wire bondability

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903114A (en) * 1985-10-01 1990-02-20 Fujitsu Limited Resin-molded semiconductor
US6251469B1 (en) 1997-03-19 2001-06-26 International Business Machines, Corporation Method of rendering a substrate selectively non-wettable chip carrier with enhanced wire bondability
US6534186B2 (en) 1997-03-19 2003-03-18 International Business Machines Corporation Chip carriers with enhanced wire bondability

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