JPH0136705B2 - - Google Patents
Info
- Publication number
- JPH0136705B2 JPH0136705B2 JP5730382A JP5730382A JPH0136705B2 JP H0136705 B2 JPH0136705 B2 JP H0136705B2 JP 5730382 A JP5730382 A JP 5730382A JP 5730382 A JP5730382 A JP 5730382A JP H0136705 B2 JPH0136705 B2 JP H0136705B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- electrode
- flip
- protruding electrodes
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 25
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 8
- 239000011347 resin Substances 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 239000010931 gold Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000011104 metalized film Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
この発明は、電極が一主面に形成されるフリツ
プチツプ形半導体チツプをパツケージあるいはキ
ヤリアに装着して構成する半導体装置に関して作
業性・信頼性向上を図つた構造を提供するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a structure that improves the workability and reliability of a semiconductor device constructed by mounting a flip-chip type semiconductor chip, in which an electrode is formed on one main surface, on a package or carrier. It is something.
以下、GaAs FETを例にとつて、この発明を
説明する。 The present invention will be explained below using a GaAs FET as an example.
第１図は、従来のフリツプチツプ形半導体チツ
プの構造を示す断面図である。フリツプチツプ形
半導体チツプ１は、第１図に示すように半導体基
体１１の一主面上にソース電極１２、ゲート電極
１３およびドレイン電極１４を設け、フリツプチ
ツプボンデイングのためにソース突起電極２１、
ゲート突起電極３１、ドレイン突起電極４１をそ
れぞれ上記ソース電極１２ゲート電極１３および
ドレイン電極１４上に備えた構造を有している。
これらの突起電極は、例えば金などの金属厚メツ
キで形成される。第２図は、フリツプチツプ形半
導体チツプ１をキヤリア５に装着した状態を示す
断面図である。キヤリア５は断面形状が凸状の金
属ベース５１上に接着用のメタライズ膜５２とフ
リツプチツプボンデイング用の金属線路５４が付
着されたセラミツク材等の絶縁物５３を接着させ
た構成を有する。第２図に示すように、これらの
半導体装置は半導体チツプ１のソース突起電極２
１、ゲート突起電極３１、ドレイン突起電極４１
とキヤリア５を対向させ、展延性に富む金属、例
えば金リボン６２，６３，６４を介して、図の矢
印の向きに示すように熱圧着することにより得ら
れていた。 FIG. 1 is a sectional view showing the structure of a conventional flip-chip type semiconductor chip. As shown in FIG. 1, the flip-chip semiconductor chip 1 includes a source electrode 12, a gate electrode 13, and a drain electrode 14 on one main surface of a semiconductor substrate 11, and a source protruding electrode 21 for flip-chip bonding.
It has a structure in which a gate protrusion electrode 31 and a drain protrusion electrode 41 are provided on the source electrode 12, gate electrode 13, and drain electrode 14, respectively.
These protruding electrodes are formed of thick metal plating, such as gold. FIG. 2 is a cross-sectional view showing the flip-chip type semiconductor chip 1 mounted on the carrier 5. As shown in FIG. The carrier 5 has a structure in which an insulating material 53 such as a ceramic material, on which a metallized film 52 for adhesion and a metal line 54 for flip-chip bonding are attached, is adhered onto a metal base 51 having a convex cross-sectional shape. As shown in FIG. 2, these semiconductor devices have a source protruding electrode 2 of a semiconductor chip 1.
1. Gate protrusion electrode 31, drain protrusion electrode 41
This was obtained by placing the carrier 5 facing each other and thermocompression bonding as shown in the direction of the arrow in the figure, using a highly malleable metal such as gold ribbons 62, 63, and 64.
しかし、従来法のAu−Auの熱圧着による方法
では、完全な接着を行なう為には比較的高い温度
と圧力をかけることが必要で、素子の信頼性の低
下を引き起こす原因となつており、また作業性が
悪いという欠点を有していた。 However, in the conventional Au-Au thermocompression bonding method, it is necessary to apply relatively high temperature and pressure to achieve complete adhesion, which causes a decrease in device reliability. It also had the disadvantage of poor workability.
本発明は上記の半導体装置の欠点に鑑みてなさ
れたもので、フリツプチツプボンデイングのため
の突起電極として金属筒状の突起電極を用い、突
起電極を除いたチツプ表面を突起電極と同じ高さ
の絶縁性樹脂でコーテイングし、金属筒状突起電
極の内側に流し込んだ半田材により、容易にかつ
接着性良くフリツプチツプボンデイングを行ない
得る半導体装置を提供するものである。 The present invention has been made in view of the above-mentioned drawbacks of semiconductor devices, and uses metal cylindrical protruding electrodes as protruding electrodes for flip-chip bonding, and the chip surface excluding the protruding electrodes is raised to the same height as the protruding electrodes. To provide a semiconductor device which can be coated with an insulating resin and subjected to flip-chip bonding easily and with good adhesiveness by using a solder material poured inside a metal cylindrical protrusion electrode.
以下、図に基づいてこの発明の一実施例を説明
する。 Hereinafter, one embodiment of the present invention will be described based on the drawings.
第４図ａ〜ｄは、この発明による半導体装置の
一実施例の製造工程の要点を示す断面図、第３図
は第４図ａの斜視図である。従つて、第４図ａは
第３図−線断面図となつている。まず、従来
と同様の方法によりソース電極１２、ゲート電極
１３およびドレイン電極１４を形成した後、第３
図および第４図ａに示すように、フリツプチツプ
ボンデイング用突起電極の高さをかせぐための筒
状突起電極７２，７３，７４を金属厚メツキによ
り形成する。続いて第４図ｂに示すように、先に
形成した突起電極７２，７３，７４を除くチツプ
表面に絶縁性樹脂８、例えばポリイミドをコーテ
イングした後、上記半導体チツプ１上に半田材を
のせることにより、絶縁性樹脂８上には半田はつ
かず、筒状突起電極７２，７３，７４の内部空間
にのみ半田材９２，９３，９４を設けることがで
きる。このようにして得られた半導体チツプ１を
半田部９５，９６，９７を介してキヤリア５に装
置することにより、フリツプチツプ形半導体装置
が完成する。 4a to 4d are cross-sectional views showing the main points of the manufacturing process of an embodiment of the semiconductor device according to the present invention, and FIG. 3 is a perspective view of FIG. 4a. Therefore, FIG. 4a is a sectional view taken along the line of FIG. 3. First, a source electrode 12, a gate electrode 13, and a drain electrode 14 are formed by a method similar to the conventional method, and then a third
As shown in the figure and FIG. 4a, cylindrical protruding electrodes 72, 73, and 74 for increasing the height of the protruding electrodes for flip-chip bonding are formed by thick metal plating. Subsequently, as shown in FIG. 4b, after coating the chip surface except for the previously formed protruding electrodes 72, 73, and 74 with an insulating resin 8, such as polyimide, a solder material is placed on the semiconductor chip 1. As a result, the solder material 92, 93, 94 can be provided only in the internal space of the cylindrical protruding electrodes 72, 73, 74 without applying solder on the insulating resin 8. The semiconductor chip 1 thus obtained is mounted on the carrier 5 via the solder portions 95, 96, 97, thereby completing a flip-chip type semiconductor device.
このようにすることにより、フリツプチツプボ
ンデイングは、従来の熱圧着から、ソフトソルダ
ーによる半田付となるので、温度は半田の融点で
良く、半田材を選ぶことにより接着温度を選ぶこ
とができるようになり、圧力に関しても従来に比
べて十分低くできるようになる。また、ボンデイ
ング用突起電極の部分以外のチツプ表面は絶縁性
樹脂でコーテイングされているため、ボンデイン
グの際に突起電極が押しつぶされて横にはみ出す
こともなく、加熱によつて半田材がメツキの外側
に流れ出すのも防ぐことができる。したがつて、
この発明の半導体装置は従来のものに比べ信頼性
向上を図ることができるようになり、作業性も良
くなるという効果がある。 By doing this, flip chip bonding changes from conventional thermocompression bonding to soldering using soft solder, so the temperature can be set to the melting point of the solder, and the bonding temperature can be selected by selecting the solder material. As a result, the pressure can be made sufficiently lower than before. In addition, since the chip surface other than the protruding electrodes for bonding is coated with insulating resin, the protruding electrodes will not be crushed and protrude sideways during bonding, and the solder material will be transferred to the outside of the plating by heating. It can also prevent water from flowing into the water. Therefore,
The semiconductor device of the present invention has the advantage of improved reliability and improved workability compared to conventional devices.
第１図は従来のフリツプチツプ形半導体チツプ
の一例を示す断面図、第２図は従来のフリツプチ
ツプ形半導体チツプをキヤリアに装着した状態を
示す断面図、第３図はソース電極、ゲート電極、
ドレイン電極の上に本発明による筒状突起電極を
設けた状態での斜視図、第４図ａ〜ｄはこの発明
による半導体装置の一実施例の製造工程を示す断
面図で、第４図ａは第３図−線断面図となつ
ている。
図に於いて、１はフリツプチツプ形半導体チツ
プ、１１は半導体基体、１２はソース電極、１３
はゲート電極、１４はドレイン電極、２１はソー
ス突起電極、３１はゲート突起電極、４１はドレ
イン突起電極、５はキヤリア、５１は金属ベー
ス、５２はメタライズ膜、５３はセラミツク材、
５４は金属線路、６２，６３，６４は金属リボ
ン、７２，７３，７４は本発明による筒状突起電
極、８は絶縁性樹脂、９２，９３，９４は半田
材、９５，９６，９７は半田部である。なお、図
中同一符号はそれぞれ同一または相当部分を示
す。
FIG. 1 is a cross-sectional view showing an example of a conventional flip-chip semiconductor chip, FIG. 2 is a cross-sectional view showing a conventional flip-chip semiconductor chip mounted on a carrier, and FIG. 3 shows a source electrode, a gate electrode,
FIGS. 4a to 4d are perspective views showing a state in which a cylindrical protrusion electrode according to the present invention is provided on a drain electrode, and FIGS. is a sectional view taken along the line in FIG. In the figure, 1 is a flip-chip type semiconductor chip, 11 is a semiconductor substrate, 12 is a source electrode, and 13 is a flip-chip type semiconductor chip.
14 is a gate electrode, 14 is a drain electrode, 21 is a source protrusion electrode, 31 is a gate protrusion electrode, 41 is a drain protrusion electrode, 5 is a carrier, 51 is a metal base, 52 is a metallized film, 53 is a ceramic material,
54 is a metal line, 62, 63, 64 is a metal ribbon, 72, 73, 74 is a cylindrical protruding electrode according to the present invention, 8 is an insulating resin, 92, 93, 94 is a solder material, 95, 96, 97 is solder Department. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
ンデイングする半導体装置において、上記半導体
チツプ上に金属からなる筒状突起電極を形成し、
この筒状突起電極を除いたチツプ表面を突起電極
と同じ高さの絶縁性樹脂層でコーテイングすると
共に、上記筒状突起電極の内部に半田材を流し込
みこの半田材を介して上記半導体チツプをキヤリ
アにボンデイングすることを特徴とする半導体装
置。1. In a semiconductor device in which a semiconductor chip is flip-chip bonded to a carrier, a cylindrical protrusion electrode made of metal is formed on the semiconductor chip,
The chip surface excluding the cylindrical protruding electrodes is coated with an insulating resin layer of the same height as the protruding electrodes, and a solder material is poured into the cylindrical protruding electrodes to carry the semiconductor chip through the solder material. A semiconductor device characterized by bonding to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5730382A JPS58175839A (en) | 1982-04-08 | 1982-04-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5730382A JPS58175839A (en) | 1982-04-08 | 1982-04-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58175839A JPS58175839A (en) | 1983-10-15 |
| JPH0136705B2 true JPH0136705B2 (en) | 1989-08-02 |
Family
ID=13051783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5730382A Granted JPS58175839A (en) | 1982-04-08 | 1982-04-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58175839A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2973691A1 (en) * | 2013-03-15 | 2016-01-20 | Microchip Technology Incorporated | Insulated top side bump connection for a power device, for example for gate, source and drain contacts of a power field effect transistor |
-
1982
- 1982-04-08 JP JP5730382A patent/JPS58175839A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2973691A1 (en) * | 2013-03-15 | 2016-01-20 | Microchip Technology Incorporated | Insulated top side bump connection for a power device, for example for gate, source and drain contacts of a power field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58175839A (en) | 1983-10-15 |
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