JPH01297829A - Semiconductor container - Google Patents

Semiconductor container

Info

Publication number
JPH01297829A
JPH01297829A JP12910088A JP12910088A JPH01297829A JP H01297829 A JPH01297829 A JP H01297829A JP 12910088 A JP12910088 A JP 12910088A JP 12910088 A JP12910088 A JP 12910088A JP H01297829 A JPH01297829 A JP H01297829A
Authority
JP
Japan
Prior art keywords
chip
container
brazing material
mount
semiconductor container
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12910088A
Other languages
Japanese (ja)
Inventor
Shuji Kanamori
金森　修二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP12910088A priority Critical patent/JPH01297829A/en
Publication of JPH01297829A publication Critical patent/JPH01297829A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent a brazing material from going around a surface upon mounting of a chip by providing a tapered portion on a container located around the chip. CONSTITUTION:A mount 1b having a taper 1a is provided on a container 1. A brazing material 2 is placed on the container 1 and melting at 400-600 deg.C to make a chip 3 adhere to the mount 1b at a given position on the mount 1b. The chip 3 is pressed and moved horizontally for bonding. Thereupon, an excessive brazing material 2 flows down from the tape 1a located around the chip. Thus, the brazing material is prevented from going around the surface of the chip. The construction makes the chip 3 fully thin. A groove is provided to the lower end of the taper 1a for preventing the brazing material from flowing out, and hence a circumference of the container is prevented from short- circuitting with an emitter-base terminal.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体容器に関し、特に、チップをマウントす
る電力用途のトランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor containers, and more particularly to transistors for power applications that mount chips.

従来の技術 従来、この種の電力用トランジスタは、コレクタ抵抗を
小さくするためにチップを薄くシて出力を補う方法を行
っていた。この種のチップのマウント法は、第３図（ａ
）、（ｂ）に示ず様に、チップ３０を鑞材２０により半
導体容器１０にマウントする技術が実用化されている５ 発明が解決しようとする課題 上述した従来のマウント方法は、チップをより薄くする
ために、マウン１〜時の余分な鑞材がチップ表面に回り
込むという欠点がある。2. Description of the Related Art Conventionally, power transistors of this type have had a chip made thin in order to reduce the collector resistance, thereby supplementing the output. The mounting method for this type of chip is shown in Figure 3 (a
), (b), a technique for mounting a chip 30 in a semiconductor container 10 using a solder material 20 has been put into practical use5.Problems to be Solved by the InventionThe conventional mounting method described above has In order to make it thinner, there is a drawback that the excess solder material from Mound 1 wraps around the chip surface.

本発明は従来の上記実情に鑑みてなされたものであり、
従って本発明の目的は、従来の技術に内在する上記欠点
を解消することを可能とした新規な半導体容器を提供す
ることにある。The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a novel semiconductor container which makes it possible to overcome the above-mentioned drawbacks inherent in the prior art.

発明の従来技術に対する相違点 上述した従来のマウント方法に対し、本発明はチップ周
辺の容器にテーパを有しているという相違点がある。Difference between the present invention and the prior art The present invention differs from the conventional mounting method described above in that the container around the chip has a taper.

課題を解決するための手段 前記目的を達成する為に、本発明に係る半導体容器は、
チップをマウン１−する領域と該半導体容器の他の部分
とにマウン１へ時の余分な鑞材をチップ周辺から分離さ
せるテーパを備えて構成される。Means for Solving the Problems In order to achieve the above object, the semiconductor container according to the present invention comprises:
The region where the chip is mounted and other parts of the semiconductor container are provided with tapers to separate excess solder material from the periphery of the chip when mounting the chip.

実施例 次に本発明をその好ましい各実施例について図面を参照
して具体的に説明する。EXAMPLES Next, preferred embodiments of the present invention will be specifically explained with reference to the drawings.

第１図（ａ）、（ｂ）は本発明による第１の実施例を示
す正面図、（ａ）のｘ−ｘ’線に沿って切断し矢印の方
向に見た縦断面図である。FIGS. 1(a) and 1(b) are a front view showing a first embodiment of the present invention, and a longitudinal sectional view taken along line xx' in FIG. 1(a) and viewed in the direction of the arrow.

第１図（ａ、）、（ｂ）を参照するに、半導体容器１に
はテーパ部１ａを有するチップマウン１〜部ｌｂが形成
されている。半導体容器１上にマウ〉・ト用鑞材２を４
００〜５００℃に加熱し溶かし、た後にデツプ３をチッ
プマウン１〜部ｌｂの所定の位置に付着させる。Referring to FIGS. 1(a) and 1(b), a semiconductor container 1 is formed with chip mounts 1 to lb having a tapered portion 1a. Place the solder material 2 for mounting on the semiconductor container 1.
After melting by heating to 00 to 500°C, the depth 3 is attached to a predetermined position of the chip mount 1 to part 1b.

このとき、チップ３とマウント用鑞材２間に気泡が出来
ない様にチップ３上から圧力をかけて、横方向に移動さ
せながら接着させるとよくなじむ様になり、余分な鑞材
２はチップ３周辺のテーパ部１ａから流れ落ちてしまう
ことになり、チップ表面に回り込むことはなくなる。At this time, apply pressure from above the chip 3 to prevent air bubbles from forming between the chip 3 and the mounting solder material 2, and move the chip 3 in the horizontal direction while adhering it. It will flow down from the taper portion 1a around the 3, and will not flow around the chip surface.

これにより、チップ厚さを充分薄くすることが可能にな
る。例えば、従来５００μｍ前後の厚さを１００μｍ程
度にすればコレクタ抵抗は厚さ分だけ減少するので、約
１，１５にすることが出来る。This makes it possible to make the chip thickness sufficiently thin. For example, if the conventional thickness is about 500 μm, if the thickness is reduced to about 100 μm, the collector resistance will be reduced by the thickness, so it can be reduced to about 1.15 μm.

第２図は本発明による第２の実施例を示す縦断面図であ
る。第２図において、この第２の実施例では余分な鑞材
２がテーパ下部より拡がりすぎて半導体容器周辺のエミ
ッタ・ベース端子に短絡しない様にテーパ部１ａの下端
部に溝４が形成されている。FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention. In FIG. 2, in this second embodiment, a groove 4 is formed at the lower end of the tapered portion 1a so that the excess solder material 2 does not spread too much from the lower part of the taper and short-circuit to the emitter/base terminal around the semiconductor container. There is.

発明の詳細 な説明した様に、本発明によれば、余分なマウント用鑞
材がチ・ツブ周辺のテーパ部に落とし込まれるのを利用
して、マウント時にチップ表面に鑞材が付着することを
防止できる効果が得られる。As described in detail, according to the present invention, by utilizing the fact that excess mounting solder material is dropped into the tapered portion around the chip, the solder material can be attached to the chip surface during mounting. The effect of preventing this can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ’）、（ｂ）は本発明に係る半導体容器の第
１の実施例を示す正面図、（ａ）のＸ−Ｘ′線に沿った
縦断面図、第２図は本発明に係る容器の第２の実施例を
示す縦断面図、第３図（ａ）、（ｂ）は従来容器の正面
図、（ａ）のＹ−Ｙ’線に沿った縦断面図である。 １、ｌＯ・・・半導体容器、１ａ・・・テーパ部、Ｉｂ
・・チップマウント部、２，２０・・・マウント用鑞材
、３，３０・・・チップ、４・・渚、５・・・エミッタ
端子、６・・・ベース端子、７・・・絶縁材 茸1(a') and (b) are front views showing a first embodiment of a semiconductor container according to the present invention, a vertical sectional view taken along the line X-X' in (a), and FIG. A vertical cross-sectional view showing a second embodiment of the container according to the invention, FIGS. 3(a) and 3(b) are a front view of a conventional container, and a vertical cross-sectional view taken along the line Y-Y' in FIG. 3(a). . 1, IO...Semiconductor container, 1a...Tapered part, Ib
...Chip mount part, 2, 20... Mounting brazing material, 3, 30... Chip, 4... Nagisa, 5... Emitter terminal, 6... Base terminal, 7... Insulating material mushroom

Claims (1)

【特許請求の範囲】[Claims] 　チップをマウントする半導体容器において、前記チッ
プをマウントする領域と該半導体容器の他の部分とにテ
ーパを有することを特徴とする半導体容器。1. A semiconductor container for mounting a chip, the semiconductor container having a taper in a region where the chip is mounted and other parts of the semiconductor container.
JP12910088A 1988-05-25 1988-05-25 Semiconductor container Pending JPH01297829A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12910088A JPH01297829A (en) 1988-05-25 1988-05-25 Semiconductor container

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12910088A JPH01297829A (en) 1988-05-25 1988-05-25 Semiconductor container

Publications (1)

Publication Number Publication Date
JPH01297829A true JPH01297829A (en) 1989-11-30

Family

ID=15001070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12910088A Pending JPH01297829A (en) 1988-05-25 1988-05-25 Semiconductor container

Country Status (1)

Country Link
JP (1) JPH01297829A (en)

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